From 203a3b3e6590d5a9c82f9f33b03a58025737b14b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 27 Nov 2018 08:57:26 +0000 Subject: [PATCH] remove trap_handled, remove w_en --- cpu.py | 2 -- cpu_handle_trap.py | 8 +------- 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/cpu.py b/cpu.py index fac67d4..b12f90e 100644 --- a/cpu.py +++ b/cpu.py @@ -269,7 +269,6 @@ class CPU(Module): # fetch action ack trap i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap), [self.handle_trap.eq(1), - self.regs.w_en.eq(0) # no writing to registers ] ) @@ -304,7 +303,6 @@ class CPU(Module): i = i.Elif((dc.act & (DA.fence | DA.fence_i | DA.store | DA.branch)) != 0, # do nothing - self.regs.w_en.eq(0) # no writing to registers ) return i diff --git a/cpu_handle_trap.py b/cpu_handle_trap.py index eaf3daf..c77be86 100644 --- a/cpu_handle_trap.py +++ b/cpu_handle_trap.py @@ -45,7 +45,6 @@ class CPUHandleTrap(Module): self.reset = ResetSignal() self.handle_trap = Signal() - self.trap_handled = Signal() self.ft_action = Signal(fetch_action) self.dc_action = Signal(decode_action) self.dc_immediate = Signal(32) @@ -102,11 +101,7 @@ class CPUHandleTrap(Module): s.append(i) - self.sync += If(self.handle_trap, - [s, self.trap_handled.eq(1)] - ).Else( - self.trap_handled.eq(0) - ) + self.sync += If(self.handle_trap, s) if __name__ == "__main__": @@ -114,7 +109,6 @@ if __name__ == "__main__": print(verilog.convert(example, { example.handle_trap, - example.trap_handled, example.ft_action, example.dc_immediate, example.mcause, -- 2.30.2