From 20407271794990b87b1a08e3ba53f45f8285e3e9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 13 Apr 2015 16:09:04 +0200 Subject: [PATCH] litesata: more pep8 (when convenient), should be almost OK --- misoclib/mem/litesata/__init__.py | 1 - misoclib/mem/litesata/core/command/__init__.py | 3 ++- misoclib/mem/litesata/core/link/__init__.py | 7 +++++-- misoclib/mem/litesata/core/link/crc.py | 1 + misoclib/mem/litesata/core/transport/__init__.py | 4 +++- misoclib/mem/litesata/phy/ctrl.py | 3 ++- misoclib/mem/litesata/phy/datapath.py | 8 ++++++-- misoclib/mem/litesata/test/crc_tb.py | 4 +++- misoclib/mem/litesata/test/hdd.py | 12 +++++++++--- misoclib/mem/litesata/test/scrambler_tb.py | 4 +++- 10 files changed, 34 insertions(+), 13 deletions(-) diff --git a/misoclib/mem/litesata/__init__.py b/misoclib/mem/litesata/__init__.py index 3839db0f..21b64293 100644 --- a/misoclib/mem/litesata/__init__.py +++ b/misoclib/mem/litesata/__init__.py @@ -19,4 +19,3 @@ class LiteSATA(Module, AutoCSR): self.submodules.crossbar = LiteSATACrossbar(self.core) if with_bist: self.submodules.bist = LiteSATABIST(self.crossbar, with_bist_csr) - diff --git a/misoclib/mem/litesata/core/command/__init__.py b/misoclib/mem/litesata/core/command/__init__.py index 3af25fa4..36a96913 100644 --- a/misoclib/mem/litesata/core/command/__init__.py +++ b/misoclib/mem/litesata/core/command/__init__.py @@ -84,7 +84,8 @@ class LiteSATACommandTX(Module): transport.sink.stb.eq(sink.stb), transport.sink.sop.eq(dwords_counter.value == 0), - transport.sink.eop.eq((dwords_counter.value == (fis_max_dwords-1)) | sink.eop), + transport.sink.eop.eq((dwords_counter.value == (fis_max_dwords-1)) | + sink.eop), sink.ack.eq(transport.sink.ack), If(sink.stb & sink.ack, diff --git a/misoclib/mem/litesata/core/link/__init__.py b/misoclib/mem/litesata/core/link/__init__.py index e8a8ca5e..a6b80f3a 100644 --- a/misoclib/mem/litesata/core/link/__init__.py +++ b/misoclib/mem/litesata/core/link/__init__.py @@ -91,7 +91,9 @@ class LiteSATALinkTX(Module): insert.eq(primitives["HOLDA"]), ).Elif(~scrambler.source.stb, insert.eq(primitives["HOLD"]), - ).Elif(scrambler.source.stb & scrambler.source.eop & scrambler.source.ack, + ).Elif(scrambler.source.stb & + scrambler.source.eop & + scrambler.source.ack, NextState("EOF") ) ) @@ -247,7 +249,8 @@ class LiteSATALink(Module): self.submodules.tx_buffer = PacketBuffer(link_description(32), buffer_depth) self.submodules.tx = LiteSATALinkTX(phy) self.submodules.rx = LiteSATALinkRX(phy) - self.submodules.rx_buffer = PacketBuffer(link_description(32), buffer_depth, almost_full=3*buffer_depth//4) + self.submodules.rx_buffer = PacketBuffer(link_description(32), buffer_depth, + almost_full=3*buffer_depth//4) self.comb += [ Record.connect(self.tx_buffer.source, self.tx.sink), Record.connect(self.rx.to_tx, self.tx.from_rx), diff --git a/misoclib/mem/litesata/core/link/crc.py b/misoclib/mem/litesata/core/link/crc.py index 8600cf99..7825a174 100644 --- a/misoclib/mem/litesata/core/link/crc.py +++ b/misoclib/mem/litesata/core/link/crc.py @@ -88,6 +88,7 @@ class LiteSATACRC(Module): polynom = 0x04C11DB7 init = 0x52325032 check = 0x00000000 + def __init__(self, dw=32): self.d = Signal(self.width) self.value = Signal(self.width) diff --git a/misoclib/mem/litesata/core/transport/__init__.py b/misoclib/mem/litesata/core/transport/__init__.py index 4375f6c1..ed19b9b1 100644 --- a/misoclib/mem/litesata/core/transport/__init__.py +++ b/misoclib/mem/litesata/core/transport/__init__.py @@ -104,7 +104,9 @@ class LiteSATATransportTX(Module): self.comb += [ counter.ce.eq(sink.stb & link.sink.ack), - cmd_done.eq((counter.value == cmd_len) & link.sink.stb & link.sink.ack), + cmd_done.eq((counter.value == cmd_len) & + link.sink.stb & + link.sink.ack), If(cmd_send, link.sink.stb.eq(sink.stb), link.sink.sop.eq(counter.value == 0), diff --git a/misoclib/mem/litesata/phy/ctrl.py b/misoclib/mem/litesata/phy/ctrl.py index fa9080d3..e73fb258 100644 --- a/misoclib/mem/litesata/phy/ctrl.py +++ b/misoclib/mem/litesata/phy/ctrl.py @@ -140,7 +140,8 @@ class LiteSATAPHYCtrl(Module): ] self.comb += \ - align_detect.eq(self.sink.stb & (self.sink.data == primitives["ALIGN"])) + align_detect.eq(self.sink.stb & + (self.sink.data == primitives["ALIGN"])) self.sync += \ If(fsm.ongoing("SEND_ALIGN"), If(sink.stb, diff --git a/misoclib/mem/litesata/phy/datapath.py b/misoclib/mem/litesata/phy/datapath.py index aad7614b..847a0d8b 100644 --- a/misoclib/mem/litesata/phy/datapath.py +++ b/misoclib/mem/litesata/phy/datapath.py @@ -20,7 +20,9 @@ class LiteSATAPHYDatapathRX(Module): last_charisk.eq(sink.charisk), last_data.eq(sink.data) ) - converter = Converter(phy_description(16), phy_description(32), reverse=False) + converter = Converter(phy_description(16), + phy_description(32), + reverse=False) converter = InsertReset(RenameClockDomains(converter, "sata_rx")) self.submodules += converter self.comb += [ @@ -71,7 +73,9 @@ class LiteSATAPHYDatapathTX(Module): self.comb += Record.connect(sink, fifo.sink) # width convertion (32 to 16) - converter = Converter(phy_description(32), phy_description(16), reverse=False) + converter = Converter(phy_description(32), + phy_description(16), + reverse=False) converter = RenameClockDomains(converter, "sata_tx") self.submodules += converter self.comb += [ diff --git a/misoclib/mem/litesata/test/crc_tb.py b/misoclib/mem/litesata/test/crc_tb.py index feccf565..237a513f 100644 --- a/misoclib/mem/litesata/test/crc_tb.py +++ b/misoclib/mem/litesata/test/crc_tb.py @@ -17,7 +17,9 @@ class TB(Module): for data in datas: stdin += "0x{:08x} ".format(data) stdin += "exit" - with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process: + with subprocess.Popen("./crc", + stdin=subprocess.PIPE, + stdout=subprocess.PIPE) as process: process.stdin.write(stdin.encode("ASCII")) out, err = process.communicate() return int(out.decode("ASCII"), 16) diff --git a/misoclib/mem/litesata/test/hdd.py b/misoclib/mem/litesata/test/hdd.py index 06cb9a2a..a9f66bfa 100644 --- a/misoclib/mem/litesata/test/hdd.py +++ b/misoclib/mem/litesata/test/hdd.py @@ -96,7 +96,9 @@ def print_link(s): def import_scrambler_datas(): - with subprocess.Popen(["./scrambler"], stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process: + with subprocess.Popen(["./scrambler"], + stdin=subprocess.PIPE, + stdout=subprocess.PIPE) as process: process.stdin.write("0x10000".encode("ASCII")) out, err = process.communicate() return [int(e, 16) for e in out.decode("utf-8").split("\n")[:-1]] @@ -121,7 +123,9 @@ class LinkRXPacket(LinkPacket): for v in self[:-1]: stdin += "0x{:08x} ".format(v) stdin += "exit" - with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process: + with subprocess.Popen("./crc", + stdin=subprocess.PIPE, + stdout=subprocess.PIPE) as process: process.stdin.write(stdin.encode("ASCII")) out, err = process.communicate() crc = int(out.decode("ASCII"), 16) @@ -140,7 +144,9 @@ class LinkTXPacket(LinkPacket): for v in self: stdin += "0x{:08x} ".foramt(v) stdin += "exit" - with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process: + with subprocess.Popen("./crc", + stdin=subprocess.PIPE, + stdout=subprocess.PIPE) as process: process.stdin.write(stdin.encode("ASCII")) out, err = process.communicate() crc = int(out.decode("ASCII"), 16) diff --git a/misoclib/mem/litesata/test/scrambler_tb.py b/misoclib/mem/litesata/test/scrambler_tb.py index 049ba353..3d36831f 100644 --- a/misoclib/mem/litesata/test/scrambler_tb.py +++ b/misoclib/mem/litesata/test/scrambler_tb.py @@ -13,7 +13,9 @@ class TB(Module): def get_c_values(self, length): stdin = "0x{:08x}".format(length) - with subprocess.Popen("./scrambler", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process: + with subprocess.Popen("./scrambler", + stdin=subprocess.PIPE, + stdout=subprocess.PIPE) as process: process.stdin.write(stdin.encode("ASCII")) out, err = process.communicate() return [int(e, 16) for e in out.decode("ASCII").split("\n")[:-1]] -- 2.30.2