From 20547491c96b37db6ceb745b1ec9b8bf5f627de0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 15 Sep 2020 20:38:37 +0100 Subject: [PATCH] comment mmu test --- src/soc/experiment/mmu.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py index 85958d54..a8c514f7 100644 --- a/src/soc/experiment/mmu.py +++ b/src/soc/experiment/mmu.py @@ -577,8 +577,9 @@ def mmu_wait(dut): l_permerr or l_rc_err or l_segerr or l_invalid): break yield - yield dut.l_in.valid.eq(0) - yield dut.l_in.mtspr.eq(0) + yield dut.l_in.valid.eq(0) # data already in MMU by now + yield dut.l_in.mtspr.eq(0) # captured by RegStage(s) + yield dut.l_in.load.eq(0) # can reset everything safely def mmu_sim(dut): global stop @@ -598,7 +599,7 @@ def mmu_sim(dut): print ("prtbl after MTSPR %x" % prtbl) assert prtbl == 0x1000000 - #yield dut.rin.prtbl.eq(0x1000000) # set process table + #yield dut.rin.prtbl.eq(0x1000000) # manually set process table #yield -- 2.30.2