From 20553b1478f03f60c1639b71a24a09a42339d352 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Alain=20P=C3=A9teut?= Date: Tue, 2 Jul 2019 10:44:12 +0200 Subject: [PATCH] build.plat: add iter_extra_files method. * vendor.*: employ iter_extra_files. --- nmigen/build/plat.py | 3 +++ nmigen/vendor/lattice_ecp5.py | 11 +++++------ nmigen/vendor/lattice_ice40.py | 11 +++++------ nmigen/vendor/xilinx_7series.py | 12 ++++-------- nmigen/vendor/xilinx_spartan6.py | 6 ++---- 5 files changed, 19 insertions(+), 24 deletions(-) diff --git a/nmigen/build/plat.py b/nmigen/build/plat.py index 7de062a..3de59f5 100644 --- a/nmigen/build/plat.py +++ b/nmigen/build/plat.py @@ -281,3 +281,6 @@ class TemplatedPlatform(Platform): for filename, content in self.extra_files.items(): plan.add_file(filename, content) return plan + + def iter_extra_files(self, *endswith): + return (f for f in self.extra_files if f.endswith(endswith)) diff --git a/nmigen/vendor/lattice_ecp5.py b/nmigen/vendor/lattice_ecp5.py index d34dbca..62a6ed5 100644 --- a/nmigen/vendor/lattice_ecp5.py +++ b/nmigen/vendor/lattice_ecp5.py @@ -67,12 +67,11 @@ class LatticeECP5Platform(TemplatedPlatform): """, "{{name}}.ys": r""" # {{autogenerated}} - {% for file in platform.extra_files %} - {% if file.endswith(".v") -%} - read_verilog {{get_override("read_opts")|join(" ")}} {{file}} - {% elif file.endswith(".sv") -%} - read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}} - {% endif %} + {% for file in platform.iter_extra_files(".v") -%} + read_verilog {{get_override("read_opts")|join(" ")}} {{file}} + {% endfor %} + {% for file in platform.iter_extra_files(".sv") -%} + read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}} {% endfor %} read_ilang {{name}}.il {{get_override("script_after_read")|default("# (script_after_read placeholder)")}} diff --git a/nmigen/vendor/lattice_ice40.py b/nmigen/vendor/lattice_ice40.py index 02c9459..73db3aa 100644 --- a/nmigen/vendor/lattice_ice40.py +++ b/nmigen/vendor/lattice_ice40.py @@ -59,12 +59,11 @@ class LatticeICE40Platform(TemplatedPlatform): """, "{{name}}.ys": r""" # {{autogenerated}} - {% for file in platform.extra_files %} - {% if file.endswith(".v") -%} - read_verilog {{get_override("read_opts")|join(" ")}} {{file}} - {% elif file.endswith(".sv") -%} - read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}} - {% endif %} + {% for file in platform.iter_extra_files(".v") -%} + read_verilog {{get_override("read_opts")|join(" ")}} {{file}} + {% endfor %} + {% for file in platform.iter_extra_files(".sv") -%} + read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}} {% endfor %} read_ilang {{name}}.il {{get_override("script_after_read")|default("# (script_after_read placeholder)")}} diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py index b0f8f99..a24f664 100644 --- a/nmigen/vendor/xilinx_7series.py +++ b/nmigen/vendor/xilinx_7series.py @@ -55,17 +55,13 @@ class Xilinx7SeriesPlatform(TemplatedPlatform): "{{name}}.tcl": r""" # {{autogenerated}} create_project -force -name {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}} - {% for file in platform.extra_files %} - {% if file.endswith((".v", ".sv")) -%} - add_files {{file}} - {% endif %} + {% for file in platform.iter_extra_files(".v", ".sv") -%} + add_files {{file}} {% endfor %} add_files {{name}}.v read_xdc {{name}}.xdc - {% for file in platform.extra_files %} - {% if file.endswith("xdc") -%} - read_xdc {{file}} - {% endif %} + {% for file in platform.iter_extra_files(".xdc") -%} + read_xdc {{file}} {% endfor %} {{get_override("script_after_read")|default("# (script_after_read placeholder)")}} synth_design -top {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}} diff --git a/nmigen/vendor/xilinx_spartan6.py b/nmigen/vendor/xilinx_spartan6.py index fef9461..5128bf9 100644 --- a/nmigen/vendor/xilinx_spartan6.py +++ b/nmigen/vendor/xilinx_spartan6.py @@ -57,10 +57,8 @@ class XilinxSpartan6Platform(TemplatedPlatform): """, "{{name}}.prj": r""" # {{autogenerated}} - {% for file in platform.extra_files -%} - {% if file.endswith(".v") %} - verilog work {{file}} - {% endif %} + {% for file in platform.iter_extra_files(".v") -%} + verilog work {{file}} {% endfor %} verilog work {{name}}.v """, -- 2.30.2