From 205b54594eb4a8614c44fe0ddf7a8e59d7076da5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 24 Jan 2022 21:23:49 +0000 Subject: [PATCH] comments --- src/soc/experiment/dcache.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index bbb655f0..4cd1c0ab 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -573,7 +573,7 @@ class DTLBUpdate(Elaboratable): # on a one-clock delay, hence the register r_tlb_way = TLBRecord("r_tlb_way") with m.If(r_delay): - # on one clock delay, output the contents of the read port(s) + # on one clock delay, capture the contents of the read port(s) comb += self.tlb_way.tag.eq(rd_tagway.data) comb += self.tlb_way.pte.eq(rd_pteway.data) sync += r_tlb_way.tag.eq(rd_tagway.data) -- 2.30.2