From 207675694c3634a76fb2614d9a4c0ac2193358e5 Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Sat, 21 Jan 2023 21:58:22 +0300 Subject: [PATCH] power_insn: hack CR assembly --- src/openpower/decoder/power_insn.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index aad06c38..df7bb4a9 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -2653,9 +2653,6 @@ class SpecifierFFPR(SpecifierPredicate): if self.record.svp64.mode is _SVMode.CROP: if self.mode == "pr": raise ValueError("crop: 'pr' mode not supported") - if (self.record.svp64.extra_CR_3bit and - (self.pred.mode is not _SVP64PredMode.RC1)): - raise ValueError("3-bit CRs only support RC1/~RC1 BO") def assemble(self, insn): selector = insn.select(record=self.record) @@ -2663,9 +2660,12 @@ class SpecifierFFPR(SpecifierPredicate): raise ValueError("cannot override mode") if self.record.svp64.mode is _SVMode.CROP: selector.mode.sel = 0b10 - selector.inv = self.pred.inv - if not self.record.svp64.extra_CR_3bit: - selector.CR = self.pred.state + # HACK: please finally provide correct logic for CRs. + if self.pred in (_SVP64Pred.RC1, _SVP64Pred.RC1_N): + selector.mode[2] = (self.pred is _SVP64Pred.RC1_N) + else: + selector.mode[2] = self.pred.inv + selector.mode[3, 4] = self.pred.state else: selector.mode.sel = 0b01 if self.mode == "ff" else 0b11 selector.inv = self.pred.inv -- 2.30.2