From 208e039bbbd854e63c4632b2085b96e8b99145f0 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 15 Mar 2013 18:18:32 +0100 Subject: [PATCH] Local clock domain example --- examples/basic/local_cd.py | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 examples/basic/local_cd.py diff --git a/examples/basic/local_cd.py b/examples/basic/local_cd.py new file mode 100644 index 00000000..ca8200a1 --- /dev/null +++ b/examples/basic/local_cd.py @@ -0,0 +1,17 @@ +from migen.fhdl.structure import * +from migen.fhdl.module import Module +from migen.fhdl import verilog +from migen.genlib.divider import Divider + +class CDM(Module): + def __init__(self): + self.submodules.divider = Divider(5) + self.clock_domains.cd_sys = ClockDomain() + +class MultiMod(Module): + def __init__(self): + self.submodules.foo = CDM() + self.submodules.bar = CDM() + +mm = MultiMod() +print(verilog.convert(mm, {mm.foo.cd_sys.clk, mm.bar.cd_sys.clk})) -- 2.30.2