From 20b472f6dcdfa216bff78e056a699a56d9bc6f65 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 24 Jan 2021 13:49:10 +0000
Subject: [PATCH]

---
 openpower/sv/svp64.mdwn | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index f3ec7a6a5..8a578031f 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -82,7 +82,7 @@ linearly to larger sizes; SV Vectorisation iterates sequentially through these r
 Where the integer regfile in standard scalar
 OpenPOWER v3.0B/v3.1B is r0 to r31, SV extends this as r0 to r127.
 Likewise FP registers are extended to 128 (fp0 to fp127), and CRs are
-extended to 64 entries, CR0 thru CR63.
+extended to 128 entries, CR0 thru CR127.
 
 The names of the registers therefore reflects a simple linear extension
 of the OpenPOWER v3.0B / v3.1B register naming, and in hardware this
-- 
2.30.2