From 20c5db02b570b946e6f029a0b5112df5376d010f Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 21 Aug 2019 11:21:05 +0200 Subject: [PATCH] ac: add has_tc_compat_zrange_bug to ac_gpu_info MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Reviewed-by: Marek Olšák --- src/amd/common/ac_gpu_info.c | 3 +++ src/amd/common/ac_gpu_info.h | 1 + src/amd/vulkan/radv_cmd_buffer.c | 4 ++-- src/amd/vulkan/radv_device.c | 2 -- src/amd/vulkan/radv_image.c | 2 +- src/amd/vulkan/radv_private.h | 1 - 6 files changed, 7 insertions(+), 6 deletions(-) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 720abb5469a..3f3a236ba80 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -470,6 +470,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, info->has_gfx9_scissor_bug = info->family == CHIP_VEGA10 || info->family == CHIP_RAVEN; + info->has_tc_compat_zrange_bug = info->chip_class >= GFX8 && + info->chip_class <= GFX9; + /* Get the number of good compute units. */ info->num_good_compute_units = 0; for (i = 0; i < info->max_se; i++) diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 0b62e37b67e..0f802216bdc 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -159,6 +159,7 @@ struct radeon_info { /* Hardware bugs. */ bool has_gfx9_scissor_bug; + bool has_tc_compat_zrange_bug; }; bool ac_query_gpu_info(int fd, void *dev_p, diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 8c7eeddd709..7031428a996 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1403,7 +1403,7 @@ radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer, uint32_t db_z_info = ds->db_z_info; uint32_t db_z_info_reg; - if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug || + if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug || !radv_image_is_tc_compat_htile(image)) return; @@ -1632,7 +1632,7 @@ radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer, { struct radeon_cmdbuf *cs = cmd_buffer->cs; - if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug) + if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug) return; uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel); diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index a34e5506463..ce487aa2eda 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -363,8 +363,6 @@ radv_physical_device_init(struct radv_physical_device *device, device->rad_info.family == CHIP_RENOIR; } - device->has_tc_compat_zrange_bug = device->rad_info.chip_class < GFX10; - device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast && !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER); diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index f0c9fd77cf6..935224c5b6d 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -1159,7 +1159,7 @@ radv_image_alloc_htile(struct radv_device *device, struct radv_image *image) image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size; image->size = image->clear_value_offset + image->info.levels * 8; if (radv_image_is_tc_compat_htile(image) && - device->physical_device->has_tc_compat_zrange_bug) { + device->physical_device->rad_info.has_tc_compat_zrange_bug) { /* Metadata for the TC-compatible HTILE hardware bug which * have to be fixed by updating ZRANGE_PRECISION when doing * fast depth clears to 0.0f. diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 55112902c34..b3d6d56e4ac 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -281,7 +281,6 @@ struct radv_physical_device { struct wsi_device wsi_device; bool rbplus_allowed; /* if RB+ is allowed */ - bool has_tc_compat_zrange_bug; bool out_of_order_rast_allowed; -- 2.30.2