From 20d600fa6cb95756dfe035760b9ec36d8d243221 Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Sun, 11 Sep 2022 23:40:40 +0300 Subject: [PATCH] power_insn: introduce pseudo cr_in2 --- src/openpower/decoder/power_enums.py | 1 + src/openpower/decoder/power_insn.py | 26 +++++++++++++++++++++++--- src/openpower/sv/sv_binutils.py | 1 + 3 files changed, 25 insertions(+), 3 deletions(-) diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index c4756806..a22a4991 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -722,6 +722,7 @@ class CRInSel(Enum): CR1 = 7 BA = 8 + @unique class CRIn2Sel(Enum): NONE = 0 diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index 1e7ff681..f76e7715 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -22,6 +22,7 @@ from openpower.decoder.power_enums import ( In3Sel as _In3Sel, OutSel as _OutSel, CRInSel as _CRInSel, + CRIn2Sel as _CRIn2Sel, CROutSel as _CROutSel, LDSTLen as _LDSTLen, LDSTMode as _LDSTMode, @@ -212,6 +213,7 @@ class PPCRecord: in3: _In3Sel = _In3Sel.NONE out: _OutSel = _OutSel.NONE cr_in: _CRInSel = _CRInSel.NONE + cr_in2: _CRIn2Sel = _CRIn2Sel.NONE cr_out: _CROutSel = _CROutSel.NONE cry_in: _CryIn = _CryIn.ZERO ldst_len: _LDSTLen = _LDSTLen.NONE @@ -237,6 +239,11 @@ class PPCRecord: typemap = {field.name:field.type for field in _dataclasses.fields(cls)} typemap["opcode"] = opcode_cls + if record["CR in"] == "BA_BB": + record["cr_in"] = "BA" + record["cr_in2"] = "BB" + del record["CR in"] + flags = set() for flag in frozenset(PPCRecord.Flags): if bool(record.pop(flag, "")): @@ -307,6 +314,7 @@ class SVP64Record: out: _OutSel = _OutSel.NONE out2: _OutSel = _OutSel.NONE cr_in: _CRInSel = _CRInSel.NONE + cr_in2: _CRIn2Sel = _CRIn2Sel.NONE cr_out: _CROutSel = _CROutSel.NONE extra: ExtraMap = ExtraMap() conditions: str = "" @@ -323,11 +331,19 @@ class SVP64Record: @classmethod def CSV(cls, record): - for key in ("in1", "in2", "in3", "out", "out2", "CR in", "CR out"): + for key in frozenset({ + "in1", "in2", "in3", "CR in", + "out", "out2", "CR out", + }): value = record[key] if value == "0": record[key] = "NONE" + if record["CR in"] == "BA_BB": + record["cr_in"] = "BA" + record["cr_in2"] = "BB" + del record["CR in"] + extra = [] for idx in range(0, 4): extra.append(record.pop(f"{idx}")) @@ -346,7 +362,7 @@ class SVP64Record: ) if key not in frozenset({ - "in1", "in2", "in3", "cr_in", + "in1", "in2", "in3", "cr_in", "cr_in2", "out", "out2", "cr_out", }): raise KeyError(key) @@ -639,7 +655,7 @@ class RegisterOperand(DynamicOperand): def extra_idx(self, record): for key in frozenset({ - "in1", "in2", "in3", "cr_in", + "in1", "in2", "in3", "cr_in", "cr_in2", "out", "out2", "cr_out", }): extra_reg = record.svp64.extra_reg(key=key) @@ -962,6 +978,10 @@ class Record: def cr_in(self): return self.ppc.cr_in + @property + def cr_in2(self): + return self.ppc.cr_in2 + @property def cr_out(self): return self.ppc.cr_out diff --git a/src/openpower/sv/sv_binutils.py b/src/openpower/sv/sv_binutils.py index 62d1a932..c026acfb 100644 --- a/src/openpower/sv/sv_binutils.py +++ b/src/openpower/sv/sv_binutils.py @@ -363,6 +363,7 @@ class Desc(Struct): out: OutSel out2: OutSel cr_in: CRInSel + cr_in2: CRInSel cr_out: CROutSel ptype: PType etype: EType -- 2.30.2