From 20d82ac37551c908039ac03a27064566e3cd65b5 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Thu, 18 Jun 2020 19:08:44 +0200 Subject: [PATCH] Add test case for delayed_enter --- gram/compat.py | 35 +++++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/gram/compat.py b/gram/compat.py index 9d183ef..2485652 100644 --- a/gram/compat.py +++ b/gram/compat.py @@ -27,11 +27,42 @@ def delayed_enter(m, src, dst, delay): with m.State(statename): m.next = deststate -# Original nMigen implementation by HarryHo90sHK +class DelayedEnterTestCase(unittest.TestCase): + def test_sequence(self): + m = Module() + + before = Signal() + end = Signal() + + with m.FSM(): + with m.State("Before-Delayed-Enter"): + m.d.comb += before.eq(1) + m.next = "Delayed-Enter" + + delayed_enter(m, "Delayed-Enter", "End-Delayed-Enter", 10) + + with m.State("End-Delayed-Enter"): + m.d.comb += end.eq(1) + + def process(): + while (yield before): + yield + delay = 0 + while not (yield end): + yield + delay += 1 + + self.assertEqual(delay, 10) + + sim = Simulator(m) + with sim.write_vcd("test_compat.vcd"): + sim.add_clock(1e-6) + sim.add_sync_process(process) + sim.run() class RoundRobin(Elaboratable): - """A round-robin scheduler. + """A round-robin scheduler. (HarryHo90sHK) Parameters ---------- n : int -- 2.30.2