From 21178877231bddb1ee806fad289b8cc7c050914a Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 14 Sep 2022 21:32:36 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls001.mdwn | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 01724ee18..431bc4306 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -20,7 +20,7 @@ and the Prefix Format is called does not add Vector opcodes or regfiles**. An ISA Concept similar to Simple-V was originally invented in 1994 by Peter Hsu (Architect of the MIPS R8000) but was dropped as MIPS did not -have an Out-of-Order Microarchitecture. +have an Out-of-Order Microarchitecture at the time. Simple-V is designed for Embedded Scenarios right the way through Audio/Visual DSPs to 3D GPUs and Supercomputing. As it does **not** @@ -58,8 +58,10 @@ at the same time*. It is also critical to note that Simple-V **does not modify the Scalar Power ISA**, that **only** Scalar words may be Vectorised, and that Vectorised instructions are **not** permitted to be -different from their Scalar words. -The sole exception to that is Vectorised +different from their Scalar words (`addi` must use the same Word encoding +as `sv.addi`, and any new Prefixed instruction added **must** also +be added as Scalar). +The sole semi-exception is Vectorised Branch Conditional, in order to provide the usual Advanced Branching capability present in every Commercial 3D GPU ISA, but it is the *Vectorised* Branch-Conditional that is augmented, not Scalar -- 2.30.2