From 212acce37305e7025a4d139957b8ffd39f420799 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 2 Mar 2023 21:33:56 -0800 Subject: [PATCH] remove trailing spaces --- openpower/sv/rfc/ls003.mdwn | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn index 86ccbaac3..3d7615a9e 100644 --- a/openpower/sv/rfc/ls003.mdwn +++ b/openpower/sv/rfc/ls003.mdwn @@ -1,4 +1,4 @@ -# RFC ls003 Big Integer +# RFC ls003 Big Integer **URLs**: @@ -81,7 +81,7 @@ TODO: address Jacob's comments: https://libre-soc.org/irclog/%23libre-soc.2022-1 1. It is not practical to add Rc=1 variants as VA-Form is used and there is a **pair** of results produced. 2. An overflow variant (XER.OV set) of `divmod2du` would be valuable - but VA-Form EXT004 is under severe pressure. + but VA-Form EXT004 is under severe pressure. 3. Both `maddhdu` and `divmod2du` instructions have been present in Intel x86 for several decades. Likewise, variants of `dsld` and `dsrd`. 4. None of these instruction is present in VSX: these are 128/64 whereas @@ -371,8 +371,8 @@ Pseudo-code: n <- (RB)[58:63] # Take lower 6-bits for shift v <- ROTL64((RA), 64-n) # Rotate RA 64-bit left by 64-n bits - mask <- MASK(n, 63) # 0's mask, set mask[n:63] to 1' - RT <- (v[0:63] & mask) | ((RC) & ¬mask) # + mask <- MASK(n, 63) # 0's mask, set mask[n:63] to 1' + RT <- (v[0:63] & mask) | ((RC) & ¬mask) # RS <- v[0:63] & ¬mask overflow = 0 if RS != [0]*64: -- 2.30.2