From 216b8a491375a3d90c7e90f48ab197e3e7d07368 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 28 Jul 2019 20:23:22 +0100
Subject: [PATCH] add signed FP2INT

---
 src/ieee754/fcvt/pipeline.py                  | 17 ++++++++++---
 src/ieee754/fcvt/test/test_fcvt_f2int_pipe.py | 25 +++++++++++++++++++
 src/ieee754/fpcommon/test/fpmux.py            |  6 +++++
 3 files changed, 44 insertions(+), 4 deletions(-)

diff --git a/src/ieee754/fcvt/pipeline.py b/src/ieee754/fcvt/pipeline.py
index eaa320bf..8f449c8b 100644
--- a/src/ieee754/fcvt/pipeline.py
+++ b/src/ieee754/fcvt/pipeline.py
@@ -105,7 +105,10 @@ class FPCVTFloatToIntMod(Elaboratable):
 
         # special cases
         with m.If(a1.is_nan):
-            m.d.comb += self.o.z.eq((1<<mz)-1) # NaN overflow
+            with m.If(signed):
+                m.d.comb += self.o.z.eq((1<<(mz-1))-1) # signed NaN overflow
+            with m.Else():
+                m.d.comb += self.o.z.eq((1<<mz)-1) # NaN overflow
 
         with m.Elif(a1.exp_n127):
             m.d.comb += self.o.z.eq(0)
@@ -141,7 +144,7 @@ class FPCVTFloatToIntMod(Elaboratable):
             m.submodules.norm_exp = msr
             m.d.comb += [msr.m_in.eq(mantissa),
                          msr.e_in.eq(a1.e),
-                         msr.ediff.eq(Mux(signed, mz-1, mz)-a1.e)
+                         msr.ediff.eq(Mux(signed, mz, mz)-a1.e)
                         ]
 
             of = Overflow()
@@ -151,10 +154,16 @@ class FPCVTFloatToIntMod(Elaboratable):
             m.d.comb += of.m0.eq(msr.m_out[3])
 
             # XXX TODO: check if this overflows the mantissa
+            mround = Signal(mlen, reset_less=True)
             with m.If(of.roundz):
-                m.d.comb += self.o.z.eq(msr.m_out[3:]+1)
+                m.d.comb += mround.eq(msr.m_out[3:]+1)
+            with m.Else():
+                m.d.comb += mround.eq(msr.m_out[3:])
+
+            with m.If(signed & a1.s):
+                m.d.comb += self.o.z.eq(-mround)
             with m.Else():
-                m.d.comb += self.o.z.eq(msr.m_out[3:])
+                m.d.comb += self.o.z.eq(mround)
 
         # copy the context (muxid, operator)
         #m.d.comb += self.o.oz.eq(self.o.z.v)
diff --git a/src/ieee754/fcvt/test/test_fcvt_f2int_pipe.py b/src/ieee754/fcvt/test/test_fcvt_f2int_pipe.py
index 3ec51258..dc48b402 100644
--- a/src/ieee754/fcvt/test/test_fcvt_f2int_pipe.py
+++ b/src/ieee754/fcvt/test/test_fcvt_f2int_pipe.py
@@ -37,6 +37,18 @@ def fcvt_f16_ui32(x):
 def fcvt_f16_ui16(x):
     return sfpy.float.f16_to_ui32(x) & 0xffff
 
+def fcvt_f16_i16(x):
+    x = sfpy.float.f16_to_i32(x)
+    if x >= 0x7fff:
+        return 0x7fff
+    if x <= -0x8000:
+        return 0x8000
+    return x & 0xffff
+
+def fcvt_f32_i32(x):
+    return sfpy.float.f32_to_i32(x) & 0xffffffff
+
+
 ######################
 # signed int to fp
 ######################
@@ -58,6 +70,16 @@ def test_int_pipe_i32_f32():
     runfp(dut, 32, "test_fcvt_int_pipe_i32_f32", to_int32, fcvt_i32_f32, True,
           n_vals=100, opcode=0x1)
 
+def test_int_pipe_f32_i32():
+    dut = FPCVTF2IntMuxInOut(32, 32, 4, op_wid=1)
+    runfp(dut, 32, "test_fcvt_f2int_pipe_f32_i32", Float32, fcvt_f32_i32,
+                True, n_vals=100, opcode=0x1)
+
+def test_int_pipe_f16_i16():
+    dut = FPCVTF2IntMuxInOut(16, 16, 4, op_wid=1)
+    runfp(dut, 16, "test_fcvt_f2int_pipe_f16_i16", Float16, fcvt_f16_i16,
+                True, n_vals=100, opcode=0x1)
+
 ######################
 # fp to unsigned int 
 ######################
@@ -115,6 +137,9 @@ def test_int_pipe_f64_ui64():
 
 if __name__ == '__main__':
     for i in range(200):
+        test_int_pipe_f16_i16()
+        test_int_pipe_f32_i32()
+        continue
         test_int_pipe_f64_ui64()
         test_int_pipe_f32_ui32()
         test_int_pipe_f16_ui16()
diff --git a/src/ieee754/fpcommon/test/fpmux.py b/src/ieee754/fpcommon/test/fpmux.py
index 028e6350..a5195c67 100644
--- a/src/ieee754/fpcommon/test/fpmux.py
+++ b/src/ieee754/fpcommon/test/fpmux.py
@@ -193,6 +193,12 @@ def create_random(num_rows, width, single_op=False, n_vals=10):
                 #op1 = 0xfcb6
                 #op1 = 0x4f8d77b3
 
+                # f2int signed
+                #op1 = 0xc913
+                #op1 = 0x7b97
+                #op1 = 0xaae2
+                #op1 = 0x7fca
+
                 # FCLASS
                 #op1 = 0x87d1
                 #op1 = 0x75e
-- 
2.30.2