From 217f61c3cb0f8be50bec4dee9f3c47db9b1eda10 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 29 Jan 2021 00:03:30 +0000 Subject: [PATCH] --- openpower/sv/implementation.mdwn | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn index b8a3491d0..88836a382 100644 --- a/openpower/sv/implementation.mdwn +++ b/openpower/sv/implementation.mdwn @@ -109,6 +109,10 @@ SV's SVSTATE context is effectively a Sub-PC. On exceptions the PC is saved int main SV for-loop, as a FSM, updating `SVSTATE.srcstep`, using it as the index in the for-loop from 0 to VL-1. Register numbers are incremented by one if marked as vector. +*This loop goes in between decode and issue phases*. It is as if there were multiple sequential instructions in the instruction stream *and the loop must be treated as such*. Specifically: all register read and write hazards **MUST** be respected; the Program Order must be respected. + +This **includes** any exceptions, hence why SVSTATE exists and why SVSRR0 must be used to store SVSTATE alongside when SRR0 and SRR1 store PC and MSR. + * ISACaller: TODO * power-gem5: TODO * TestIssuer: TODO -- 2.30.2