From 218df2948363cb9d4a7a455d2b755562f085fd9e Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 10 Apr 2022 17:09:58 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 8b7ca773a..e69bf86bb 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -360,12 +360,20 @@ a cumulative series of overlapping add operations into the Execution units of the underlying hardware. Other examples include shift-mask operations where a Vector of inserts -into a single destination register is required, as a way to construct +into a single destination register is required (see [[sv/bitmanip]], bmset), +as a way to construct a value quickly from multiple arbitrary bit-ranges and bit-offsets. Using the same register as both the source and destination, with Vectors of different offsets masks and values to be inserted has multiple applications including Video, cryptography and JIT compilation. + # assume VL=4: + # * Vector of shift-offsets contained in RC (r12.v) + # * Vector of masks contained in RB (r8.v) + # * Vector of values to be masked-in in RA (r4.v) + # * Scalar destination RT (r0) to receive all mask-offset values + sv.bmset/mr r0, r4.v, r8.v, r12.v + Due to the Deterministic Scheduling, Subtract and Divide are still permitted to be executed in this mode, although from an algorithmic perspective it is strongly discouraged. -- 2.30.2