From 21a1e0b121a740cc4da8b6b6e64bde2b154925da Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 3 Jun 2020 14:07:21 +0100 Subject: [PATCH] add class containing all regfiles --- src/soc/regfile/regfiles.py | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py index d44242a5..dc92f0c4 100644 --- a/src/soc/regfile/regfiles.py +++ b/src/soc/regfile/regfiles.py @@ -126,3 +126,13 @@ class SPRRegs(RegFile): super().__init__(64, n_sprs) self.w_ports = [self.write_port("dest")] self.r_ports = [self.read_port("src")] + + +class RegFiles: + def __init__(self): + self.int = IntRegs() + self.cr = CRRegs() + self.xer = XERRegs() + self.fasr = FastRegs() + self.spr = SPRRegs() + -- 2.30.2