From 21a28d950b800465a0ea1a1cc0c5d9ac0903c3bb Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 22 Jun 2019 09:23:55 +0100 Subject: [PATCH] --- simple_v_extension/sv_prefix_proposal.rst | 28 ++++++++++++++++------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/simple_v_extension/sv_prefix_proposal.rst b/simple_v_extension/sv_prefix_proposal.rst index 0f0f18046..fc1922fe1 100644 --- a/simple_v_extension/sv_prefix_proposal.rst +++ b/simple_v_extension/sv_prefix_proposal.rst @@ -128,23 +128,35 @@ TODO (please disregard) +--------------+-------+-------+--------+--------+--------+----------+ | Encoding | 63:58 | 57 | 56 | 55 | 54 | 53:48 | +--------------+-------+-------+--------+--------+--------+----------+ -| P64-LD-type | VL | rd[6] | rs1[6] | | | Vstart | +| P64-LD-type | VLtyp | rd[6] | rs1[6] | | | MVLtp | +--------------+-------+-------+--------+--------+--------+----------+ -| P64-ST-type | VL | | rs1[6] | rs2[6] | | Vstart | +| P64-ST-type | VLtyp | | rs1[6] | rs2[6] | | MVLtp | +--------------+-------+-------+--------+--------+--------+----------+ -| P64-R-type | VL | rd[6] | rs1[6] | rs2[6] | | Vstart | +| P64-R-type | VLtyp | rd[6] | rs1[6] | rs2[6] | | MVLtp | +--------------+-------+-------+--------+--------+--------+----------+ -| P64-I-type | VL | rd[6] | rs1[6] | | | Vstart | +| P64-I-type | VLtyp | rd[6] | rs1[6] | | | MVLtp | +--------------+-------+-------+--------+--------+--------+----------+ -| P64-U-type | VL | rd[6] | | | | Vstart | +| P64-U-type | VLtyp | rd[6] | | | | MVLtp | +--------------+-------+-------+--------+--------+--------+----------+ -| P64-FR-type | VL | | rs1[6] | rs2[6] | | Vstart | +| P64-FR-type | VLtyp | | rs1[6] | rs2[6] | | MVLtp | +--------------+-------+-------+--------+--------+--------+----------+ -| P64-FI-type | VL | rd[6] | rs1[6] | rs2[6] | | Vstart | +| P64-FI-type | VLtyp | rd[6] | rs1[6] | rs2[6] | | MVLtp | +--------------+-------+-------+--------+--------+--------+----------+ -| P64-FR4-type | VL | rd[6] | rs1[6] | rs2[6] | rs3[6] | Vstart | +| P64-FR4-type | VLtyp | rd[6] | rs1[6] | rs2[6] | rs3[6] | MVLtp | +--------------+-------+-------+--------+--------+--------+----------+ +VLtyp + ++--------------+---------+ +| vtyp[5:1] | vtyp[0] | ++--------------+---------+ +| regnum | 1 | ++--------------+---------+ +| immed | 0 | ++--------------+---------+ + +Just as in the VLIW format, when bit 0 of vtyp is zero, bits 1 to 5 specify the scalar register that VL is set from. When bit 0 is 1, VL is set to the immediate (plus one). + vs#/vd Fields' Encoding ======================= -- 2.30.2