From 21a6103a73c3ef5c4cc1f0c21a19df2b5961b705 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 22 May 2021 11:36:16 +0000 Subject: [PATCH] annoying rename of pll analog pin --- .../full_core_4_4ksram_litex_ls180.v | 70 +++++++++---------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v b/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v index 758f193..871cf53 100644 --- a/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v +++ b/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v @@ -1,7 +1,23 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-05-22 11:51:10 +// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-05-22 12:34:49 //-------------------------------------------------------------------------------- module ls180( + output wire i2c_scl, + input wire i2c_sda_i, + output wire i2c_sda_o, + output wire i2c_sda_oe, + input wire [15:0] gpio_i, + output wire [15:0] gpio_o, + output wire [15:0] gpio_oe, + output wire spimaster_clk, + output wire spimaster_mosi, + output wire spimaster_cs_n, + input wire spimaster_miso, + input wire uart_tx, + input wire uart_rx, + input wire eint_0, + input wire eint_1, + input wire eint_2, output wire [12:0] sdram_a, input wire [15:0] sdram_dq_i, output wire [15:0] sdram_dq_o, @@ -14,22 +30,6 @@ module ls180( output wire [1:0] sdram_ba, output wire [1:0] sdram_dm, output wire sdram_clock, - output wire i2c_scl, - input wire i2c_sda_i, - output wire i2c_sda_o, - output wire i2c_sda_oe, - input wire eint_0, - input wire eint_1, - input wire eint_2, - output wire spimaster_clk, - output wire spimaster_mosi, - output wire spimaster_cs_n, - input wire spimaster_miso, - input wire uart_tx, - input wire uart_rx, - input wire [15:0] gpio_i, - output wire [15:0] gpio_o, - output wire [15:0] gpio_oe, input wire sys_clk, input wire sys_rst, input wire [1:0] sys_clksel_i, @@ -159,6 +159,22 @@ wire [63:0] libresocsim_libresoc3; wire libresocsim_libresoc_pll_18_o; wire [1:0] libresocsim_libresoc_clk_sel; wire libresocsim_libresoc_pll_ana_o; +wire libresocsim_libresoc_constraintmanager_i2c_scl; +wire libresocsim_libresoc_constraintmanager_i2c_sda_i; +wire libresocsim_libresoc_constraintmanager_i2c_sda_o; +wire libresocsim_libresoc_constraintmanager_i2c_sda_oe; +wire [15:0] libresocsim_libresoc_constraintmanager_gpio_i; +reg [15:0] libresocsim_libresoc_constraintmanager_gpio_o = 16'd0; +reg [15:0] libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0; +reg libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0; +reg libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0; +reg libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0; +wire libresocsim_libresoc_constraintmanager_spimaster_miso; +reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1; +reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0; +wire libresocsim_libresoc_constraintmanager_eint_0; +wire libresocsim_libresoc_constraintmanager_eint_1; +wire libresocsim_libresoc_constraintmanager_eint_2; reg [12:0] libresocsim_libresoc_constraintmanager_sdram_a = 13'd0; wire [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_i; reg [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_o = 16'd0; @@ -171,22 +187,6 @@ reg libresocsim_libresoc_constraintmanager_sdram_cke = 1'd0; reg [1:0] libresocsim_libresoc_constraintmanager_sdram_ba = 2'd0; reg [1:0] libresocsim_libresoc_constraintmanager_sdram_dm = 2'd0; reg libresocsim_libresoc_constraintmanager_sdram_clock = 1'd0; -wire libresocsim_libresoc_constraintmanager_i2c_scl; -wire libresocsim_libresoc_constraintmanager_i2c_sda_i; -wire libresocsim_libresoc_constraintmanager_i2c_sda_o; -wire libresocsim_libresoc_constraintmanager_i2c_sda_oe; -wire libresocsim_libresoc_constraintmanager_eint_0; -wire libresocsim_libresoc_constraintmanager_eint_1; -wire libresocsim_libresoc_constraintmanager_eint_2; -reg libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0; -reg libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0; -reg libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0; -wire libresocsim_libresoc_constraintmanager_spimaster_miso; -reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1; -reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0; -wire [15:0] libresocsim_libresoc_constraintmanager_gpio_i; -reg [15:0] libresocsim_libresoc_constraintmanager_gpio_o = 16'd0; -reg [15:0] libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0; reg [29:0] libresocsim_interface0_converted_interface_adr = 30'd0; reg [31:0] libresocsim_interface0_converted_interface_dat_w = 32'd0; wire [31:0] libresocsim_interface0_converted_interface_dat_r; @@ -6085,6 +6085,7 @@ test_issuer test_issuer( .mtwi_sda__pad__oe(i2c_sda_oe), .pc_o(libresocsim_libresoc3), .pll_18_o(libresocsim_libresoc_pll_18_o), + .pll_testout_o(libresocsim_libresoc_pll_ana_o), .sdr_a_0__pad__o(sdram_a[0]), .sdr_a_10__pad__o(sdram_a[10]), .sdr_a_11__pad__o(sdram_a[11]), @@ -6167,8 +6168,7 @@ test_issuer test_issuer( .sram4k_2_wb__err(libresocsim_libresoc_interface2_err), .sram4k_3_wb__ack(libresocsim_libresoc_interface3_ack), .sram4k_3_wb__dat_r(libresocsim_libresoc_interface3_dat_r), - .sram4k_3_wb__err(libresocsim_libresoc_interface3_err), - .vco_test_ana(libresocsim_libresoc_pll_ana_o) + .sram4k_3_wb__err(libresocsim_libresoc_interface3_err) ); endmodule -- 2.30.2