From 21b92b3464193a203e069f50c21ebec146ae0215 Mon Sep 17 00:00:00 2001 From: Pierre Moreau Date: Tue, 5 Dec 2017 00:51:04 +0100 Subject: [PATCH] nvir: Always split 64-bit IMAD/IMUL operations Those operations do not map to actual hardware instructions, therefore those should always be lowered to 32-bit instructions. Fixes: 009c54aa7af "nv50/ir: Split 64-bit integer MAD/MUL operations" Signed-off-by: Pierre Moreau Reviewed-by: Karol Herbst Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp index ecb4bae2a83..d851cf3c37c 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp @@ -3986,7 +3986,7 @@ Program::optimizeSSA(int level) RUN_PASS(2, AlgebraicOpt, run); RUN_PASS(2, ModifierFolding, run); // before load propagation -> less checks RUN_PASS(1, ConstantFolding, foldAll); - RUN_PASS(1, Split64BitOpPreRA, run); + RUN_PASS(0, Split64BitOpPreRA, run); RUN_PASS(2, LateAlgebraicOpt, run); RUN_PASS(1, LoadPropagation, run); RUN_PASS(1, IndirectPropagation, run); -- 2.30.2