From 21eb96a6e9843486c423e86e5b46d6075ee74c20 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 24 Oct 2023 18:16:06 +0100 Subject: [PATCH] whitespace cleanup --- src/openpower/decoder/isa/test_syscall.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/openpower/decoder/isa/test_syscall.py b/src/openpower/decoder/isa/test_syscall.py index 6c782409..a1f42ba2 100644 --- a/src/openpower/decoder/isa/test_syscall.py +++ b/src/openpower/decoder/isa/test_syscall.py @@ -70,7 +70,7 @@ class SyscallTestCase(FHDLTestCase): self.assertEqual(sim.msr, MSR) # MSR changed to this by sc/trap print("SYSCALL SRR1", hex(int(SRR1)), hex(int(sim.spr['SRR1']))) - print("SYSCALL MSR", hex(int(MSR)), hex(int(sim.msr)), hex(DEFAULT_MSR)) + print("SYSCALL MSR", hex(int(MSR)), hex(int(sim.msr)), hex(DEFAULT_MSR)) return sim def test_sc_getpid(self): -- 2.30.2