From 21f2bb22a3077dce5ce8e93a0bebc9a9b7fdb82d Mon Sep 17 00:00:00 2001 From: =?utf8?q?Nicolai=20H=C3=A4hnle?= Date: Tue, 29 Nov 2016 15:53:19 +0100 Subject: [PATCH] radeonsi: do not export VS outputs from vertex streams != 0 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This affects for GS copy shaders. When an output is meant for vertex stream != 0, then we don't have to make it available to the pixel shader. There is a minor inefficiency here because the GLSL varying packing pass does not group varyings of the same vertex stream together, but it shouldn't be important in practice. Reviewed-by: Marek Olšák --- src/gallium/drivers/radeonsi/si_shader.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 5a40c5ee91d..7c8fad1d659 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -2394,6 +2394,12 @@ static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base, break; } + if (outputs[i].vertex_stream[0] != 0 && + outputs[i].vertex_stream[1] != 0 && + outputs[i].vertex_stream[2] != 0 && + outputs[i].vertex_stream[3] != 0) + export_param = false; + handle_semantic: /* Select the correct target */ switch(semantic_name) { -- 2.30.2