From 21f79a8d22f675519404114bdc412ffa5cd40fed Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 25 Jul 2020 22:18:18 +0100 Subject: [PATCH] whoops one extra bit on the overflow test in mullw/mulld --- openpower/isa/fixedarith.mdwn | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openpower/isa/fixedarith.mdwn b/openpower/isa/fixedarith.mdwn index 7edafee2d..a3d054aac 100644 --- a/openpower/isa/fixedarith.mdwn +++ b/openpower/isa/fixedarith.mdwn @@ -350,8 +350,8 @@ Pseudo-code: prod[0:63] <- MULS((RA)[32:63], (RB)[32:63]) RT <- prod - overflow <- ((prod[0:32] != 0x0_0000_0000) & - (prod[0:32] != 0x1_ffff_ffff)) + overflow <- ((prod[0:33] != 0x0_0000_0000) & + (prod[0:33] != 0x1_ffff_ffff)) Special Registers Altered: @@ -564,8 +564,8 @@ Pseudo-code: prod[0:127] <- MULS((RA), (RB)) RT <- prod[64:127] - overflow <- ((prod[0:64] != 0x0_0000_0000_0000_0000) & - (prod[0:64] != 0x1_ffff_ffff_ffff_ffff)) + overflow <- ((prod[0:65] != 0x0_0000_0000_0000_0000) & + (prod[0:65] != 0x1_ffff_ffff_ffff_ffff)) Special Registers Altered: -- 2.30.2