From 22190c01654269e6f4964f7295df6af73cb8d100 Mon Sep 17 00:00:00 2001
From: Michael LeBeane <Michael.Lebeane@amd.com>
Date: Wed, 9 May 2018 17:02:17 -0400
Subject: [PATCH] arch-gcn3: Fix V_MAD_I32_I24 sign extension

We are not properly sign extending the bits we hack off for
V_MAD_I32_I24.

This fixes rnn_fwdBwd 64 1 1 lstm pte assertion failure.

Change-Id: I2516e5715227cbd822e6a62630674f64f7a109e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29928
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/gcn3/insts/instructions.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/arch/gcn3/insts/instructions.cc b/src/arch/gcn3/insts/instructions.cc
index 32719ad27..0256d469b 100644
--- a/src/arch/gcn3/insts/instructions.cc
+++ b/src/arch/gcn3/insts/instructions.cc
@@ -27446,8 +27446,8 @@ namespace Gcn3ISA
 
         for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
             if (wf->execMask(lane)) {
-                vdst[lane] = bits(src0[lane], 23, 0) * bits(src1[lane], 23, 0)
-                    + src2[lane];
+                vdst[lane] = sext<24>(bits(src0[lane], 23, 0))
+                    * sext<24>(bits(src1[lane], 23, 0)) + src2[lane];
             }
         }
 
-- 
2.30.2