From 22507b117c1d591504c5010c3b54364febf872e7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 10 Oct 2014 20:45:18 +0200 Subject: [PATCH] bank: add re to CSRStorage being able to know when a register is updated is useful in many cases and avoid having to handle another register for that. re is asserted when the the last CSR of the Compound is written. Software must also write Compound in the right order. --- migen/bank/description.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/migen/bank/description.py b/migen/bank/description.py index 7bb3b95a..fd506fe2 100644 --- a/migen/bank/description.py +++ b/migen/bank/description.py @@ -53,6 +53,7 @@ class CSRStorage(_CompoundCSR): self.storage = Signal(self.size - self.alignment_bits, reset=reset >> alignment_bits) self.comb += self.storage.eq(self.storage_full[self.alignment_bits:]) self.atomic_write = atomic_write + self.re = Signal() if write_from_dev: self.we = Signal() self.dat_w = Signal(self.size - self.alignment_bits) @@ -84,6 +85,7 @@ class CSRStorage(_CompoundCSR): self.sync += If(sc.re, self.storage_full.eq(Cat(sc.r, backstore))) else: self.sync += If(sc.re, self.storage_full[lo:hi].eq(sc.r)) + self.sync += self.re.eq(sc.re) def csrprefix(prefix, csrs, done): for csr in csrs: -- 2.30.2