From 225a2d4704cdf0abf7a9a1d53a1b2b2f0cb8a3bc Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 27 Feb 2015 14:12:13 +0100 Subject: [PATCH] report cachesize in wishbone2lasmi --- migen/bus/wishbone2lasmi.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/migen/bus/wishbone2lasmi.py b/migen/bus/wishbone2lasmi.py index 404b88ac..a2110caf 100644 --- a/migen/bus/wishbone2lasmi.py +++ b/migen/bus/wishbone2lasmi.py @@ -1,12 +1,14 @@ from migen.fhdl.std import * from migen.bus import wishbone +from migen.bank.description import * from migen.genlib.fsm import FSM, NextState from migen.genlib.misc import split, displacer, chooser from migen.genlib.record import Record, layout_len # cachesize (in 32-bit words) is the size of the data store, must be a power of 2 -class WB2LASMI(Module): +class WB2LASMI(Module, AutoCSR): def __init__(self, cachesize, lasmim): + self._cachesize = CSRStatus(8, reset=log2_int(cachesize)) self.wishbone = wishbone.Interface() ### -- 2.30.2