From 226d9eef9fa5dd58dc3a638d630c2920146f5746 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 26 Dec 2020 03:09:56 +0000 Subject: [PATCH] --- openpower/sv/overview.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index d4051aad1..7d6f03888 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -434,7 +434,7 @@ The only one missing from the list here, because it is non-sequential, is VGATHER: moving registers by specifying a vector of register indices (`regs[rd] = regs[regs[rs]]` in a loop). This one is tricky because it typically does not exist in standard scalar ISAs. If it did it would -be called [[sv/mv.x]] +be called [[sv/mv.x]]. Once Vectorised, it's a VGATHER. # CR predicate result analysis -- 2.30.2