From 22746aeb180b2ea5f358f7f3cbcf1c39ffa29436 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 30 Sep 2020 09:43:40 +0100 Subject: [PATCH] forgot to add PLRUs as submodules --- src/soc/experiment/icache.py | 4 ++-- src/soc/experiment/plru.py | 10 +++++----- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index c1d98371..4fb56dcf 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -713,11 +713,11 @@ class ICache(Elaboratable): for i in range(NUM_LINES): plru_acc_i = Signal(WAY_BITS) plru_acc_en = Signal() - plru_out = Signal(WAY_BITS) plru = PLRU(WAY_BITS) + setattr(m.submodules, "plru_%d" % i, plru) + comb += plru.acc_i.eq(plru_acc_i) comb += plru.acc_en.eq(plru_acc_en) - comb += plru.lru_o.eq(plru_out) # PLRU interface with m.If(get_index(r.hit_nia) == i): diff --git a/src/soc/experiment/plru.py b/src/soc/experiment/plru.py index 99e51f6d..31f84c20 100644 --- a/src/soc/experiment/plru.py +++ b/src/soc/experiment/plru.py @@ -1,6 +1,6 @@ # based on microwatt plru.vhdl -from nmigen import Elaboratable, Signal, Array, Module, Mux +from nmigen import Elaboratable, Signal, Array, Module, Mux, Const from nmigen.cli import rtlil @@ -21,9 +21,9 @@ class PLRU(Elaboratable): # XXX Check if we can turn that into a little ROM instead that # takes the tree bit vector and returns the LRU. See if it's better # in term of FPGA resouces usage... - node = Const(0, self.bits) + node = Const(0, self.BITS) for i in range(self.BITS): - # report "GET: i:" & integer'image(i) & " node:" & + # report "GET: i:" & integer'image(i) & " node:" & # integer'image(node) & " val:" & Signal()'image(tree(node)) comb += self.lru_o[self.BITS-1-i].eq(tree[node]) if i != self.BITS-1: @@ -34,9 +34,9 @@ class PLRU(Elaboratable): node = node_next with m.If(self.acc_en): - node = Const(0, self.bits) + node = Const(0, self.BITS) for i in range(self.BITS): - # report "GET: i:" & integer'image(i) & " node:" & + # report "GET: i:" & integer'image(i) & " node:" & # integer'image(node) & " val:" & Signal()'image(tree(node)) abit = self.acc_i[self.BITS-1-i] sync += tree[node].eq(~abit) -- 2.30.2