From 22bf31a7e2ef3a7195911d78707ffdde0c5f365a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 11 Sep 2022 14:04:16 +0100 Subject: [PATCH] shorten words --- openpower/sv/rfc/ls001.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 82c87a6a1..33072e9d9 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -125,7 +125,7 @@ such large numbers of registers, even for Multi-Issue microarchitectures. * No new Interrupt types are required. (**No modifications to existing Power ISA are required either**). -* GPR FPR and CR Field Register numbers are extended to 128. A future +* GPR FPR and CR Field Register extend to 128. A future version may extend to 256 or beyond[^extend] or also extend VSX[^futurevsx] * 24-bits are needed within the main SVP64 Prefix (equivalent to a 2-bit XO) * Another 24-bit (a second 2-bit XO) is needed for a planned future encoding, -- 2.30.2