From 22c4700827c9ac1788c919b5a85d860412d77ff3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 12 May 2021 13:04:37 +0100 Subject: [PATCH] no need for sel0 --- src/soc/experiment/cache_ram.py | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/soc/experiment/cache_ram.py b/src/soc/experiment/cache_ram.py index 4f7e4705..71dc89ca 100644 --- a/src/soc/experiment/cache_ram.py +++ b/src/soc/experiment/cache_ram.py @@ -31,10 +31,8 @@ class CacheRam(Elaboratable): rd_data0 = Signal(WIDTH) - sel0 = Signal(WIDTH//8) # defaults to zero - with m.If(TRACE): - with m.If(self.wr_sel != sel0): + with m.If(self.wr_sel.bool()): sync += Display( "write a: %x sel: %x dat: %x", self.wr_addr, self.wr_sel, self.wr_data) for i in range(WIDTH//8): -- 2.30.2