From 22d3e047e570b098729a982901b5338b997c80a0 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 11 Mar 2020 08:51:08 +0100 Subject: [PATCH] radv: use better tessellation tunables on GFX9+ Based on PAL and RadeonSI. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/si_cmd_buffer.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index c846d0ac002..08defa83bb9 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -420,7 +420,14 @@ si_emit_graphics(struct radv_physical_device *physical_device, S_030980_NUM_PC_LINES(128 * physical_device->rad_info.max_se - 1)); } - if (physical_device->rad_info.chip_class >= GFX8) { + if (physical_device->rad_info.chip_class >= GFX9) { + radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION, + S_028B50_ACCUM_ISOLINE(40) | + S_028B50_ACCUM_TRI(30) | + S_028B50_ACCUM_QUAD(24) | + S_028B50_DONUT_SPLIT(24) | + S_028B50_TRAP_SPLIT(6)); + } else if (physical_device->rad_info.chip_class >= GFX8) { uint32_t vgt_tess_distribution; vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) | -- 2.30.2