From 2303fb7735b0fab0786821d0fb6fe40a49dd8367 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 12 Sep 2022 17:27:16 +0100 Subject: [PATCH] --- openpower/sv/sprs.mdwn | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/openpower/sv/sprs.mdwn b/openpower/sv/sprs.mdwn index 5bda4fa41..08c36e0d4 100644 --- a/openpower/sv/sprs.mdwn +++ b/openpower/sv/sprs.mdwn @@ -51,6 +51,8 @@ full context save/restore (see SVSRR0). It contains (and permits setting of): instruction unless this bit is set, in which case REMAP "persists". Reset (cleared) on use of the `setvl` instruction if used to alter VL or MVL. +* Pack - if set then srcstep/substep VL/SUBVL loop-ordering is inverted. +* UnPack - if set then dststep/substep VL/SUBVL loop-ordering is inverted. * hphint - Horizontal Parallelism Hint. Indicates that no Hazards exist between these elements. In Vertical First Mode hardware **MUST** perform this many elements in parallel @@ -127,7 +129,9 @@ The format of the SVSTATE SPR is as follows: | 38:39 | mo0 | REMAP RT SVSHAPE0-3 | | 40:41 | mo1 | REMAP EA SVSHAPE0-3 | | 42:46 | SVme | REMAP enable (RA-RT) | -| 47:t4 | rsvd | reserved | +| 47:52 | rsvd | reserved | +| 53 | pack | PACK (srcstrp reorder) | +| 54 | unpack | UNPACK (dststep order) | | 55:61 | hphint | Horizontal Hint | | 62 | RMpst | REMAP persistence | | 63 | vfirst | Vertical First mode | -- 2.30.2