From 2378d5d604dfacea50e7147acceb928cb04555de Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 28 Apr 2023 11:50:53 +0100 Subject: [PATCH] --- openpower/sv/sprs.mdwn | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/openpower/sv/sprs.mdwn b/openpower/sv/sprs.mdwn index 78f6a61b9..243f7ebd4 100644 --- a/openpower/sv/sprs.mdwn +++ b/openpower/sv/sprs.mdwn @@ -108,6 +108,22 @@ could be adversely affected. SVP64 purely relies on Scalar instructions, so Scalar instructions (except the SVP64 Management ones and mtspr and mfspr) are 100% guaranteed to have zero impact on SVP64 state. +**SVme REMAP area** + +Each bit of `SVSTATE.SVme` indicates whether the SVSHAPE (0-3) is active and to which register +the REMAP applies. The application goes by *assembler operand names* on a per-mnemonic +basis. Some instructions may have `RT` as a source and as a destination: REMAP applies +**separately** to each use in this case. Also for Load/Store with Update the Effective +Address (stored in EA) also may be separately REMAPed from RA as a source operand. + +| bit|applies|register applied| +|----|-------|----------------| +| 46 | mi0 | source RA / FRA / BA / BFA / RT / FRT | +| 45 | mi1 | source RB / FRB / BB| +| 44 | mi2 | source RC / FRC / BC| +| 43 | mo0 | result RT / FRT / BT / BF| +| 42 | mo1 | result Effective Address (RA) / FRS / RS| + **Max Vector Length (maxvl)** MAXVECTORLENGTH is a static (immediate-operand only) compile-time declaration -- 2.30.2