From 237962debd9fcb7e9fb45f53bc8a53f0c34d9888 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 13 May 2020 13:33:37 -0700 Subject: [PATCH] verilog: default to input in sv mode if task/func has no dir ... otherwise error --- frontends/verilog/verilog_parser.y | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index b7c6af91e..f250d7685 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -855,8 +855,16 @@ task_func_port: frontend_verilog_yyerror("task/function argument range must be of the form: [:], [+:], or [-:]"); } wire_name | { - if (!astbuf1) - frontend_verilog_yyerror("Non-ANSI style task/function arguments not currently supported"); + if (!astbuf1) { + if (!sv_mode) + frontend_verilog_yyerror("task/function argument direction missing"); + albuf = new dict; + astbuf1 = new AstNode(AST_WIRE); + current_wire_rand = false; + current_wire_const = false; + astbuf1->is_input = true; + astbuf2 = NULL; + } } wire_name; task_func_body: -- 2.30.2