From 239b33e016b19aa18e70f3bc64c4e11de3f92c7d Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 2 Nov 2011 01:25:15 -0700 Subject: [PATCH] SE/FS: Get rid of FULL_SYSTEM in the ARM ISA. --- src/arch/arm/SConscript | 15 +++--- src/arch/arm/faults.cc | 79 ++++++++++++++------------- src/arch/arm/faults.hh | 17 +++--- src/arch/arm/insts/static_inst.hh | 7 +-- src/arch/arm/isa/formats/data.isa | 2 - src/arch/arm/isa/formats/m5ops.isa | 8 --- src/arch/arm/isa/formats/unimp.isa | 9 ++-- src/arch/arm/isa/insts/div.isa | 18 +++---- src/arch/arm/isa/insts/m5ops.isa | 18 ------- src/arch/arm/isa/insts/misc.isa | 51 ++++++++---------- src/arch/arm/isa/insts/neon.isa | 41 +++++++------- src/arch/arm/isa/insts/swap.isa | 9 ++-- src/arch/arm/remote_gdb.cc | 48 ++++++++--------- src/arch/arm/tlb.cc | 29 +++++----- src/arch/arm/utility.cc | 87 +++++++++++++++--------------- 15 files changed, 192 insertions(+), 246 deletions(-) diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index daa083a22..171c04718 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -56,11 +56,16 @@ if env['TARGET_ISA'] == 'arm': Source('insts/vfp.cc') Source('interrupts.cc') Source('isa.cc') + Source('linux/linux.cc') + Source('linux/process.cc') + Source('linux/system.cc') Source('miscregs.cc') Source('nativetrace.cc') Source('predecoder.cc') + Source('process.cc') Source('remote_gdb.cc') Source('stacktrace.cc') + Source('system.cc') Source('table_walker.cc') Source('tlb.cc') Source('utility.cc') @@ -68,21 +73,13 @@ if env['TARGET_ISA'] == 'arm': SimObject('ArmInterrupts.py') SimObject('ArmNativeTrace.py') + SimObject('ArmSystem.py') SimObject('ArmTLB.py') DebugFlag('Arm') DebugFlag('TLBVerbose') DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi") DebugFlag('Predecoder', "Instructions returned by the predecoder") - if env['FULL_SYSTEM']: - Source('system.cc') - Source('linux/system.cc') - - SimObject('ArmSystem.py') - else: - Source('process.cc') - Source('linux/linux.cc') - Source('linux/process.cc') # Add in files generated by the ISA description. isa_desc_files = env.ISADesc('isa/main.isa') diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index 68c5fa0e8..52441e03f 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -47,6 +47,7 @@ #include "cpu/base.hh" #include "cpu/thread_context.hh" #include "debug/Faults.hh" +#include "sim/full_system.hh" namespace ArmISA { @@ -94,13 +95,13 @@ ArmFault::getVector(ThreadContext *tc) } -#if FULL_SYSTEM - void ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst) { // ARM ARM B1.6.3 FaultBase::invoke(tc); + if (!FullSystem) + return; countStat()++; SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); @@ -165,48 +166,54 @@ ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst) void Reset::invoke(ThreadContext *tc, StaticInstPtr inst) { - tc->getCpuPtr()->clearInterrupts(); - tc->clearArchRegs(); + if (FullSystem) { + tc->getCpuPtr()->clearInterrupts(); + tc->clearArchRegs(); + } ArmFault::invoke(tc, inst); } -#else - void UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst) { - // If the mnemonic isn't defined this has to be an unknown instruction. - assert(unknown || mnemonic != NULL); - if (disabled) { - panic("Attempted to execute disabled instruction " - "'%s' (inst 0x%08x)", mnemonic, machInst); - } else if (unknown) { - panic("Attempted to execute unknown instruction (inst 0x%08x)", - machInst); + if (FullSystem) { + ArmFault::invoke(tc, inst); } else { - panic("Attempted to execute unimplemented instruction " - "'%s' (inst 0x%08x)", mnemonic, machInst); + // If the mnemonic isn't defined this has to be an unknown instruction. + assert(unknown || mnemonic != NULL); + if (disabled) { + panic("Attempted to execute disabled instruction " + "'%s' (inst 0x%08x)", mnemonic, machInst); + } else if (unknown) { + panic("Attempted to execute unknown instruction (inst 0x%08x)", + machInst); + } else { + panic("Attempted to execute unimplemented instruction " + "'%s' (inst 0x%08x)", mnemonic, machInst); + } } } void SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst) { - // As of now, there isn't a 32 bit thumb version of this instruction. - assert(!machInst.bigThumb); - uint32_t callNum; - callNum = tc->readIntReg(INTREG_R7); - tc->syscall(callNum); - - // Advance the PC since that won't happen automatically. - PCState pc = tc->pcState(); - assert(inst); - inst->advancePC(pc); - tc->pcState(pc); + if (FullSystem) { + ArmFault::invoke(tc, inst); + } else { + // As of now, there isn't a 32 bit thumb version of this instruction. + assert(!machInst.bigThumb); + uint32_t callNum; + callNum = tc->readIntReg(INTREG_R7); + tc->syscall(callNum); + + // Advance the PC since that won't happen automatically. + PCState pc = tc->pcState(); + assert(inst); + inst->advancePC(pc); + tc->pcState(pc); + } } -#endif // FULL_SYSTEM - template void AbortFault::invoke(ThreadContext *tc, StaticInstPtr inst) @@ -245,13 +252,13 @@ template void AbortFault::invoke(ThreadContext *tc, void ArmSev::invoke(ThreadContext *tc, StaticInstPtr inst) { DPRINTF(Faults, "Invoking ArmSev Fault\n"); -#if FULL_SYSTEM - // Set sev_mailbox to 1, clear the pending interrupt from remote - // SEV execution and let pipeline continue as pcState is still - // valid. - tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); - tc->getCpuPtr()->clearInterrupt(INT_SEV, 0); -#endif + if (FullSystem) { + // Set sev_mailbox to 1, clear the pending interrupt from remote + // SEV execution and let pipeline continue as pcState is still + // valid. + tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); + tc->getCpuPtr()->clearInterrupt(INT_SEV, 0); + } } // return via SUBS pc, lr, xxx; rfe, movs, ldm diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index 2d025cc94..9858e52ef 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -48,8 +48,8 @@ #include "arch/arm/miscregs.hh" #include "arch/arm/types.hh" #include "base/misc.hh" -#include "config/full_system.hh" #include "sim/faults.hh" +#include "sim/full_system.hh" // The design of the "name" and "vect" functions is in sim/faults.hh @@ -108,10 +108,8 @@ class ArmFault : public FaultBase FaultStat count; }; -#if FULL_SYSTEM void invoke(ThreadContext *tc, StaticInstPtr inst = StaticInst::nullStaticInstPtr); -#endif virtual FaultStat& countStat() = 0; virtual FaultOffset offset() = 0; virtual OperatingMode nextMode() = 0; @@ -139,19 +137,14 @@ class ArmFaultVals : public ArmFault }; class Reset : public ArmFaultVals -#if FULL_SYSTEM { public: void invoke(ThreadContext *tc, StaticInstPtr inst = StaticInst::nullStaticInstPtr); }; -#else -{}; -#endif //FULL_SYSTEM class UndefinedInstruction : public ArmFaultVals { -#if !FULL_SYSTEM protected: ExtMachInst machInst; bool unknown; @@ -167,25 +160,27 @@ class UndefinedInstruction : public ArmFaultVals mnemonic(_mnemonic), disabled(_disabled) { } + UndefinedInstruction() : + machInst(0), unknown(false), mnemonic("undefined"), disabled(false) + {} void invoke(ThreadContext *tc, StaticInstPtr inst = StaticInst::nullStaticInstPtr); -#endif }; class SupervisorCall : public ArmFaultVals { -#if !FULL_SYSTEM protected: ExtMachInst machInst; public: SupervisorCall(ExtMachInst _machInst) : machInst(_machInst) {} + SupervisorCall() : machInst(0) + {} void invoke(ThreadContext *tc, StaticInstPtr inst = StaticInst::nullStaticInstPtr); -#endif }; template diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh index fa850190f..d65555822 100644 --- a/src/arch/arm/insts/static_inst.hh +++ b/src/arch/arm/insts/static_inst.hh @@ -46,6 +46,7 @@ #include "arch/arm/utility.hh" #include "base/trace.hh" #include "cpu/static_inst.hh" +#include "sim/full_system.hh" namespace ArmISA { @@ -294,11 +295,11 @@ class ArmStaticInst : public StaticInst inline Fault disabledFault() const { -#if FULL_SYSTEM + if (FullSystem) { return new UndefinedInstruction(); -#else + } else { return new UndefinedInstruction(machInst, false, mnemonic, true); -#endif + } } }; } diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa index 03a585001..ffe5f45e3 100644 --- a/src/arch/arm/isa/formats/data.isa +++ b/src/arch/arm/isa/formats/data.isa @@ -1103,7 +1103,6 @@ def format ArmMisc() {{ switch (IMM) { case 0x0: return new NopInst(machInst); -#if FULL_SYSTEM case 0x1: return new YieldInst(machInst); case 0x2: @@ -1112,7 +1111,6 @@ def format ArmMisc() {{ return new WfiInst(machInst); case 0x4: return new SevInst(machInst); -#endif default: return new Unknown(machInst); } diff --git a/src/arch/arm/isa/formats/m5ops.isa b/src/arch/arm/isa/formats/m5ops.isa index f532d828b..3b08acad7 100644 --- a/src/arch/arm/isa/formats/m5ops.isa +++ b/src/arch/arm/isa/formats/m5ops.isa @@ -42,35 +42,27 @@ def format M5ops() {{ { const uint32_t m5func = bits(machInst, 23, 16); switch(m5func) { -#if FULL_SYSTEM case 0x00: return new Arm(machInst); case 0x01: return new Quiesce(machInst); case 0x02: return new QuiesceNs(machInst); case 0x03: return new QuiesceCycles(machInst); case 0x04: return new QuiesceTime(machInst); -#endif case 0x07: return new Rpns(machInst); case 0x09: return new WakeCPU(machInst); case 0x10: return new Deprecated_ivlb(machInst); case 0x11: return new Deprecated_ivle(machInst); case 0x20: return new Deprecated_exit (machInst); case 0x21: return new M5exit(machInst); -#if FULL_SYSTEM case 0x31: return new Loadsymbol(machInst); case 0x30: return new Initparam(machInst); -#endif case 0x40: return new Resetstats(machInst); case 0x41: return new Dumpstats(machInst); case 0x42: return new Dumpresetstats(machInst); case 0x43: return new M5checkpoint(machInst); -#if FULL_SYSTEM case 0x50: return new M5readfile(machInst); -#endif case 0x51: return new M5break(machInst); case 0x52: return new M5switchcpu(machInst); -#if FULL_SYSTEM case 0x53: return new M5addsymbol(machInst); -#endif case 0x54: return new M5panic(machInst); case 0x5a: return new M5workbegin(machInst); case 0x5b: return new M5workend(machInst); diff --git a/src/arch/arm/isa/formats/unimp.isa b/src/arch/arm/isa/formats/unimp.isa index a0e0afd32..1c9a4b402 100644 --- a/src/arch/arm/isa/formats/unimp.isa +++ b/src/arch/arm/isa/formats/unimp.isa @@ -147,11 +147,10 @@ output exec {{ FailUnimplemented::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { -#if FULL_SYSTEM - return new UndefinedInstruction; -#else - return new UndefinedInstruction(machInst, false, mnemonic); -#endif + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(machInst, false, mnemonic); } Fault diff --git a/src/arch/arm/isa/insts/div.isa b/src/arch/arm/isa/insts/div.isa index 8a94d1ebd..1ff6ef9e4 100644 --- a/src/arch/arm/isa/insts/div.isa +++ b/src/arch/arm/isa/insts/div.isa @@ -41,11 +41,10 @@ let {{ sdivCode = ''' if (Op2_sw == 0) { if (((SCTLR)Sctlr).dz) { -#if FULL_SYSTEM - return new UndefinedInstruction; -#else - return new UndefinedInstruction(false, mnemonic); -#endif + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(false, mnemonic); } Dest_sw = 0; } else if (Op1_sw == INT_MIN && Op2_sw == -1) { @@ -65,11 +64,10 @@ let {{ udivCode = ''' if (Op2_uw == 0) { if (((SCTLR)Sctlr).dz) { -#if FULL_SYSTEM - return new UndefinedInstruction; -#else - return new UndefinedInstruction(false, mnemonic); -#endif + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(false, mnemonic); } Dest_uw = 0; } else { diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa index e891a0a91..a157b414c 100644 --- a/src/arch/arm/isa/insts/m5ops.isa +++ b/src/arch/arm/isa/insts/m5ops.isa @@ -54,9 +54,7 @@ let {{ armCode = ''' -#if FULL_SYSTEM PseudoInst::arm(xc->tcBase()); -#endif ''' armIop = InstObjParams("arm", "Arm", "PredOp", { "code": armCode, @@ -67,9 +65,7 @@ let {{ exec_output += PredOpExecute.subst(armIop) quiesceCode = ''' -#if FULL_SYSTEM PseudoInst::quiesce(xc->tcBase()); -#endif ''' quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp", { "code": quiesceCode, @@ -80,9 +76,7 @@ let {{ exec_output += QuiescePredOpExecute.subst(quiesceIop) quiesceNsCode = ''' -#if FULL_SYSTEM PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0)); -#endif ''' quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp", @@ -94,9 +88,7 @@ let {{ exec_output += QuiescePredOpExecute.subst(quiesceNsIop) quiesceCyclesCode = ''' -#if FULL_SYSTEM PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0)); -#endif ''' quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp", @@ -108,11 +100,9 @@ let {{ exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop) quiesceTimeCode = ''' -#if FULL_SYSTEM uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase()); R0 = bits(qt_val, 31, 0); R1 = bits(qt_val, 63, 32); -#endif ''' quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp", @@ -188,9 +178,7 @@ let {{ exec_output += PredOpExecute.subst(m5exitIop) loadsymbolCode = ''' -#if FULL_SYSTEM PseudoInst::loadsymbol(xc->tcBase()); -#endif ''' loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp", @@ -202,9 +190,7 @@ let {{ exec_output += PredOpExecute.subst(loadsymbolIop) initparamCode = ''' -#if FULL_SYSTEM Rt = PseudoInst::initParam(xc->tcBase()); -#endif ''' initparamIop = InstObjParams("initparam", "Initparam", "PredOp", @@ -260,11 +246,9 @@ let {{ exec_output += PredOpExecute.subst(m5checkpointIop) m5readfileCode = ''' -#if FULL_SYSTEM int n = 4; uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false); R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset); -#endif ''' m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp", { "code": m5readfileCode, @@ -291,9 +275,7 @@ let {{ exec_output += PredOpExecute.subst(m5switchcpuIop) m5addsymbolCode = ''' -#if FULL_SYSTEM PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2); -#endif ''' m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp", { "code": m5addsymbolCode, diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 2cf54fcdb..495cb722c 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -40,11 +40,11 @@ let {{ svcCode = ''' -#if FULL_SYSTEM - fault = new SupervisorCall; -#else - fault = new SupervisorCall(machInst); -#endif + if (FullSystem) { + fault = new SupervisorCall; + } else { + fault = new SupervisorCall(machInst); + } ''' svcIop = InstObjParams("svc", "Svc", "PredOp", @@ -501,7 +501,6 @@ let {{ exec_output += PredOpExecute.subst(yieldIop) wfeCode = ''' -#if FULL_SYSTEM // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending if (SevMailbox == 1) { SevMailbox = 0; @@ -511,14 +510,11 @@ let {{ } else { PseudoInst::quiesce(xc->tcBase()); } -#endif ''' wfePredFixUpCode = ''' -#if FULL_SYSTEM // WFE is predicated false, reset SevMailbox to reduce spurious sleeps // and SEV interrupts SevMailbox = 1; -#endif ''' wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ { "code" : wfeCode, @@ -530,14 +526,12 @@ let {{ exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop) wfiCode = ''' -#if FULL_SYSTEM // WFI doesn't sleep if interrupts are pending (masked or not) if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) { PseudoInst::quiesceSkip(xc->tcBase()); } else { PseudoInst::quiesce(xc->tcBase()); } -#endif ''' wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ { "code" : wfiCode, "predicate_test" : predicateTest }, @@ -547,7 +541,6 @@ let {{ exec_output += QuiescePredOpExecute.subst(wfiIop) sevCode = ''' -#if FULL_SYSTEM SevMailbox = 1; System *sys = xc->tcBase()->getSystemPtr(); for (int x = 0; x < sys->numContexts(); x++) { @@ -560,7 +553,6 @@ let {{ oc->getCpuPtr()->postInterrupt(INT_SEV, 0); } } -#endif ''' sevIop = InstObjParams("sev", "SevInst", "PredOp", \ { "code" : sevCode, "predicate_test" : predicateTest }, @@ -577,11 +569,10 @@ let {{ decoder_output += BasicConstructor.subst(itIop) exec_output += PredOpExecute.subst(itIop) unknownCode = ''' -#if FULL_SYSTEM - return new UndefinedInstruction; -#else - return new UndefinedInstruction(machInst, true); -#endif + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(machInst, true); ''' unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \ { "code": unknownCode, @@ -634,12 +625,12 @@ let {{ mrc15code = ''' CPSR cpsr = Cpsr; - if (cpsr.mode == MODE_USER) -#if FULL_SYSTEM - return new UndefinedInstruction; -#else - return new UndefinedInstruction(false, mnemonic); -#endif + if (cpsr.mode == MODE_USER) { + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(false, mnemonic); + } Dest = MiscOp1; ''' @@ -653,12 +644,12 @@ let {{ mcr15code = ''' CPSR cpsr = Cpsr; - if (cpsr.mode == MODE_USER) -#if FULL_SYSTEM - return new UndefinedInstruction; -#else - return new UndefinedInstruction(false, mnemonic); -#endif + if (cpsr.mode == MODE_USER) { + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(false, mnemonic); + } MiscDest = Op1; ''' mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp", diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa index fdb6237c0..9565ee14a 100644 --- a/src/arch/arm/isa/insts/neon.isa +++ b/src/arch/arm/isa/insts/neon.isa @@ -872,11 +872,10 @@ let {{ readDestCode = 'destElem = gtoh(destReg.elements[i]);' eWalkCode += ''' if (imm < 0 && imm >= eCount) { -#if FULL_SYSTEM - fault = new UndefinedInstruction; -#else - fault = new UndefinedInstruction(false, mnemonic); -#endif + if (FullSystem) + fault = new UndefinedInstruction; + else + fault = new UndefinedInstruction(false, mnemonic); } else { for (unsigned i = 0; i < eCount; i++) { Element srcElem1 = gtoh(srcReg1.elements[i]); @@ -927,11 +926,10 @@ let {{ readDestCode = 'destElem = gtoh(destReg.elements[i]);' eWalkCode += ''' if (imm < 0 && imm >= eCount) { -#if FULL_SYSTEM - fault = new UndefinedInstruction; -#else - fault = new UndefinedInstruction(false, mnemonic); -#endif + if (FullSystem) + fault = new UndefinedInstruction; + else + fault = new UndefinedInstruction(false, mnemonic); } else { for (unsigned i = 0; i < eCount; i++) { Element srcElem1 = gtoh(srcReg1.elements[i]); @@ -980,11 +978,10 @@ let {{ readDestCode = 'destReg = destRegs[i];' eWalkCode += ''' if (imm < 0 && imm >= eCount) { -#if FULL_SYSTEM - fault = new UndefinedInstruction; -#else - fault = new UndefinedInstruction(false, mnemonic); -#endif + if (FullSystem) + fault = new UndefinedInstruction; + else + fault = new UndefinedInstruction(false, mnemonic); } else { for (unsigned i = 0; i < rCount; i++) { FloatReg srcReg1 = srcRegs1[i]; @@ -3298,14 +3295,14 @@ let {{ destReg.elements[i] = srcReg1.elements[index]; } else { index -= eCount; - if (index >= eCount) -#if FULL_SYSTEM - fault = new UndefinedInstruction; -#else - fault = new UndefinedInstruction(false, mnemonic); -#endif - else + if (index >= eCount) { + if (FullSystem) + fault = new UndefinedInstruction; + else + fault = new UndefinedInstruction(false, mnemonic); + } else { destReg.elements[i] = srcReg2.elements[index]; + } } } ''' diff --git a/src/arch/arm/isa/insts/swap.isa b/src/arch/arm/isa/insts/swap.isa index f319e75aa..b42a1c4b2 100644 --- a/src/arch/arm/isa/insts/swap.isa +++ b/src/arch/arm/isa/insts/swap.isa @@ -73,11 +73,10 @@ let {{ swpPreAccCode = ''' if (!((SCTLR)Sctlr).sw) { -#if FULL_SYSTEM - return new UndefinedInstruction; -#else - return new UndefinedInstruction(false, mnemonic); -#endif + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(false, mnemonic); } ''' diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc index 223ff4c69..528e19acf 100644 --- a/src/arch/arm/remote_gdb.cc +++ b/src/arch/arm/remote_gdb.cc @@ -134,11 +134,6 @@ #include -#include "config/full_system.hh" -#if FULL_SYSTEM -#include "arch/arm/vtophys.hh" -#endif - #include "arch/arm/pagetable.hh" #include "arch/arm/registers.hh" #include "arch/arm/remote_gdb.hh" @@ -157,6 +152,7 @@ #include "mem/page_table.hh" #include "mem/physical.hh" #include "mem/port.hh" +#include "sim/full_system.hh" #include "sim/system.hh" using namespace std; @@ -173,28 +169,28 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc) bool RemoteGDB::acc(Addr va, size_t len) { -#if FULL_SYSTEM - Addr last_va; - va = truncPage(va); - last_va = roundPage(va + len); - - do { - if (virtvalid(context, va)) { - return true; - } - va += PageBytes; - } while (va < last_va); - - DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va); - return true; -#else - TlbEntry entry; - //Check to make sure the first byte is mapped into the processes address - //space. - if (context->getProcessPtr()->pTable->lookup(va, entry)) + if (FullSystem) { + Addr last_va; + va = truncPage(va); + last_va = roundPage(va + len); + + do { + if (virtvalid(context, va)) { + return true; + } + va += PageBytes; + } while (va < last_va); + + DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va); return true; - return false; -#endif + } else { + TlbEntry entry; + //Check to make sure the first byte is mapped into the processes address + //space. + if (context->getProcessPtr()->pTable->lookup(va, entry)) + return true; + return false; + } } /* diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index f824925f2..6953090d0 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -47,6 +47,7 @@ #include "arch/arm/faults.hh" #include "arch/arm/pagetable.hh" +#include "arch/arm/system.hh" #include "arch/arm/table_walker.hh" #include "arch/arm/tlb.hh" #include "arch/arm/utility.hh" @@ -62,10 +63,6 @@ #include "sim/full_system.hh" #include "sim/process.hh" -#if FULL_SYSTEM -#include "arch/arm/system.hh" -#endif - using namespace std; using namespace ArmISA; @@ -421,14 +418,14 @@ TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, } } -#if !FULL_SYSTEM - Addr paddr; - Process *p = tc->getProcessPtr(); + if (!FullSystem) { + Addr paddr; + Process *p = tc->getProcessPtr(); - if (!p->pTable->translate(vaddr, paddr)) - return Fault(new GenericPageTableFault(vaddr)); - req->setPaddr(paddr); -#endif + if (!p->pTable->translate(vaddr, paddr)) + return Fault(new GenericPageTableFault(vaddr)); + req->setPaddr(paddr); + } return NoFault; } @@ -573,11 +570,11 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, } } -#if FULL_SYSTEM - if (!bootUncacheability && - ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr)) - req->setFlags(Request::UNCACHEABLE); -#endif + if (FullSystem) { + if (!bootUncacheability && + ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr)) + req->setFlags(Request::UNCACHEABLE); + } switch ( (dacr >> (te->domain * 2)) & 0x3) { case 0: diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index bbba38d2b..6c2997a27 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -40,15 +40,12 @@ #include "arch/arm/faults.hh" #include "arch/arm/isa_traits.hh" +#include "arch/arm/tlb.hh" #include "arch/arm/utility.hh" -#include "cpu/thread_context.hh" - -#if FULL_SYSTEM #include "arch/arm/vtophys.hh" +#include "cpu/thread_context.hh" #include "mem/vport.hh" -#endif - -#include "arch/arm/tlb.hh" +#include "sim/full_system.hh" namespace ArmISA { @@ -66,49 +63,49 @@ initCPU(ThreadContext *tc, int cpuId) uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) { -#if FULL_SYSTEM - if (size == (uint16_t)(-1)) - size = ArmISA::MachineBytes; - if (fp) - panic("getArgument(): Floating point arguments not implemented\n"); - - if (number < NumArgumentRegs) { - // If the argument is 64 bits, it must be in an even regiser number - // Increment the number here if it isn't even - if (size == sizeof(uint64_t)) { - if ((number % 2) != 0) - number++; - // Read the two halves of the data - // number is inc here to get the second half of the 64 bit reg - uint64_t tmp; - tmp = tc->readIntReg(number++); - tmp |= tc->readIntReg(number) << 32; - return tmp; + if (FullSystem) { + if (size == (uint16_t)(-1)) + size = ArmISA::MachineBytes; + if (fp) + panic("getArgument(): Floating point arguments not implemented\n"); + + if (number < NumArgumentRegs) { + // If the argument is 64 bits, it must be in an even regiser + // number. Increment the number here if it isn't even. + if (size == sizeof(uint64_t)) { + if ((number % 2) != 0) + number++; + // Read the two halves of the data. Number is inc here to + // get the second half of the 64 bit reg. + uint64_t tmp; + tmp = tc->readIntReg(number++); + tmp |= tc->readIntReg(number) << 32; + return tmp; + } else { + return tc->readIntReg(number); + } } else { - return tc->readIntReg(number); - } - } else { - Addr sp = tc->readIntReg(StackPointerReg); - VirtualPort *vp = tc->getVirtPort(); - uint64_t arg; - if (size == sizeof(uint64_t)) { - // If the argument is even it must be aligned - if ((number % 2) != 0) + Addr sp = tc->readIntReg(StackPointerReg); + VirtualPort *vp = tc->getVirtPort(); + uint64_t arg; + if (size == sizeof(uint64_t)) { + // If the argument is even it must be aligned + if ((number % 2) != 0) + number++; + arg = vp->read(sp + + (number-NumArgumentRegs) * sizeof(uint32_t)); + // since two 32 bit args == 1 64 bit arg, increment number number++; - arg = vp->read(sp + - (number-NumArgumentRegs) * sizeof(uint32_t)); - // since two 32 bit args == 1 64 bit arg, increment number - number++; - } else { - arg = vp->read(sp + - (number-NumArgumentRegs) * sizeof(uint32_t)); + } else { + arg = vp->read(sp + + (number-NumArgumentRegs) * sizeof(uint32_t)); + } + return arg; } - return arg; + } else { + panic("getArgument() only implemented for full system mode.\n"); + M5_DUMMY_RETURN } -#else - panic("getArgument() only implemented for FULL_SYSTEM\n"); - M5_DUMMY_RETURN -#endif } void -- 2.30.2