From 23b5ac23677036c14f027dc094edf18e906c7e13 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 3 Jul 2022 19:24:33 +0100 Subject: [PATCH] add biginteger analysis chapter --- openpower/Makefile | 6 ++++++ openpower/simple_v_spec.tex | 4 ++++ openpower/sv.mdwn | 17 ++++++++++------- 3 files changed, 20 insertions(+), 7 deletions(-) diff --git a/openpower/Makefile b/openpower/Makefile index 677684dc8..b85af2e2e 100755 --- a/openpower/Makefile +++ b/openpower/Makefile @@ -78,6 +78,12 @@ tex: pandoc -f markdown -t latex --top-level-division=section \ --filter pandoc_img.py \ -N -o tex_out/av_opcodes.tex sv/av_opcodes.mdwn + pandoc -f markdown -t latex --top-level-division=section \ + --filter pandoc_img.py \ + -N -o tex_out/big_integer.tex sv/biginteger.mdwn + pandoc -f markdown -t latex --top-level-division=section \ + --filter pandoc_img.py \ + -N -o tex_out/big_integer_analysis.tex sv/biginteger/analysis.mdwn pdf: diff --git a/openpower/simple_v_spec.tex b/openpower/simple_v_spec.tex index a31dbb7b9..0012227c9 100644 --- a/openpower/simple_v_spec.tex +++ b/openpower/simple_v_spec.tex @@ -200,6 +200,10 @@ Programme, requires full transparency. \input{tex_out/int_fp_mv.tex} \chapter{Audio/Video ops}\hypertarget{svux2fav_opcodes}{} \input{tex_out/av_opcodes.tex} +\chapter{Big Integer}\hypertarget{svux2fbiginteger}{} +\input{tex_out/big_integer.tex} +\chapter{Big Integer}\hypertarget{svux2fbigintegerux2fanalysis}{} +\input{tex_out/big_integer_analysis.tex} diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn index fa14bc4d3..3b13a5940 100644 --- a/openpower/sv.mdwn +++ b/openpower/sv.mdwn @@ -168,15 +168,18 @@ Stand-alone Scalar Instructions: * [[sv/fclass]] detect class of FP numbers * [[sv/int_fp_mv]] Move and convert GPR <-> FPR, needed for !VSX * [[sv/av_opcodes]] scalar opcodes for Audio/Video -* Twin targetted instructions (two registers out, one implicit, just like - Load-with-Update). - Explanation of the rules for twin register targets - (implicit RS, FRS) explained in SVP64 [[svp64/appendix]] - - [[isa/svfixedarith]] - - [[isa/svfparith]] - - [[sv/biginteger]] Operations that help with big arithmetic * TODO: OpenPOWER adaptation [[openpower/transcendentals]] +Twin targetted instructions (two registers out, one implicit, just like +Load-with-Update). + +* [[isa/svfixedarith]] +* [[isa/svfparith]] +* [[sv/biginteger]] Operations that help with big arithmetic + +Explanation of the rules for twin register targets +(implicit RS, FRS) explained in SVP64 [[svp64/appendix]] + # Other Scalable Vector ISAs These Scalable Vector ISAs are listed to aid in understanding and -- 2.30.2