From 23ba1ccb52915242184a8b33a9ae1dc2c993d819 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 1 May 2015 16:16:48 +0200 Subject: [PATCH] targets/minispartan6: add USBSoC (working, should also be usable on pipistrello) --- targets/minispartan6.py | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/targets/minispartan6.py b/targets/minispartan6.py index e1a04ad4..94e4cad6 100644 --- a/targets/minispartan6.py +++ b/targets/minispartan6.py @@ -2,12 +2,17 @@ from fractions import Fraction from migen.fhdl.std import * from migen.genlib.resetsync import AsyncResetSynchronizer +from migen.actorlib.fifo import SyncFIFO from misoclib.mem.sdram.module import AS4C16M16 from misoclib.mem.sdram.phy import gensdrphy from misoclib.mem.sdram.core.lasmicon import LASMIconSettings from misoclib.soc.sdram import SDRAMSoC +from misoclib.com.liteusb.common import * +from misoclib.com.liteusb.phy.ft245 import FT245PHY +from misoclib.com.liteusb.core import LiteUSBCore +from misoclib.com.liteusb.frontend.uart import LiteUSBUART class _CRG(Module): def __init__(self, platform, clk_freq): @@ -77,4 +82,36 @@ class BaseSoC(SDRAMSoC): AS4C16M16(clk_freq)) self.register_sdram_phy(self.sdrphy) + +class USBSoC(BaseSoC): + csr_map = { + "usb_dma": 16, + } + csr_map.update(BaseSoC.csr_map) + + usb_map = { + "uart": 0, + "dma": 1 + } + + def __init__(self, platform, **kwargs): + BaseSoC.__init__(self, platform, with_uart=False, **kwargs) + + self.submodules.usb_phy = FT245PHY(platform.request("usb_fifo"), self.clk_freq) + self.submodules.usb_core = LiteUSBCore(self.usb_phy, self.clk_freq, with_crc=False) + + # UART + usb_uart_port = self.usb_core.crossbar.get_port(self.usb_map["uart"]) + self.submodules.uart = LiteUSBUART(usb_uart_port) + + # DMA + usb_dma_port = self.usb_core.crossbar.get_port(self.usb_map["dma"]) + usb_dma_loopback_fifo = SyncFIFO(user_description(8), 1024, buffered=True) + self.submodules += usb_dma_loopback_fifo + self.comb += [ + usb_dma_port.source.connect(usb_dma_loopback_fifo.sink), + usb_dma_loopback_fifo.source.connect(usb_dma_port.sink) + ] + default_subtarget = BaseSoC + -- 2.30.2