From 23bad0712788e3fbb2dc7767628456297aeac4ef Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 25 Nov 2018 10:20:49 +0000
Subject: [PATCH] add MISA and MIE

---
 cpu.py | 230 +++++++++++++++++++++------------------------------------
 1 file changed, 85 insertions(+), 145 deletions(-)

diff --git a/cpu.py b/cpu.py
index 3bce542..4fbeafe 100644
--- a/cpu.py
+++ b/cpu.py
@@ -26,6 +26,7 @@
 `include "cpu.vh"
 """
 
+import string
 from migen import *
 from migen.fhdl import verilog
 from migen.fhdl.structure import _Operator
@@ -58,8 +59,9 @@ class Decoder:
     act = Signal(decode_action, name="decoder_action")
 
 class MStatus:
-    def __init__(self, comb):
+    def __init__(self, comb, sync):
         self.comb = comb
+        self.sync = sync
         self.mpie = Signal(name="mstatus_mpie")
         self.mie = Signal(name="mstatus_mie")
         self.mprv = Signal(name="mstatus_mprv")
@@ -78,11 +80,62 @@ class MStatus:
         self.uie = Signal(name="mstatus_uie")
 
         for n in dir(self):
-            if n in ['mpp', 'comb'] or n.startswith("_"):
+            if n in ['mpp', 'comb', 'sync'] or n.startswith("_"):
                 continue
             self.comb += getattr(self, n).eq(0x0)
         self.comb += self.mpp.eq(0b11)
 
+        self.sync += self.mie.eq(0)
+        self.sync += self.mpie.eq(0)
+
+class MIE:
+    def __init__(self, comb, sync):
+        self.comb = comb
+        self.sync = sync
+        self.meie = Signal(name="mie_meie")
+        self.mtie = Signal(name="mie_mtie")
+        self.msie = Signal(name="mie_msie")
+        self.ueie = Signal(name="mie_ueie")
+        self.stie = Signal(name="mie_stie")
+        self.utie = Signal(name="mie_utie")
+        self.ssie = Signal(name="mie_ssie")
+        self.usie = Signal(name="mie_usie")
+
+        for n in dir(self):
+            if n in ['comb', 'sync'] or n.startswith("_"):
+                continue
+            self.comb += getattr(self, n).eq(0x0)
+
+        self.sync += self.meie.eq(0)
+        self.sync += self.mtie.eq(0)
+        self.sync += self.msie.eq(0)
+
+
+class M:
+    def __init__(self, comb, sync):
+        self.comb = comb
+        self.sync = sync
+        self.mcause = Signal(32)
+        self.mepc = Signal(32)
+        self.mscratch = Signal(32)
+        self.sync += self.mcause.eq(0)
+        self.sync += self.mepc.eq(0) # 32'hXXXXXXXX;
+        self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX;
+
+class Misa:
+
+    def __init__(self, comb, sync):
+        self.comb = comb
+        self.sync = sync
+        self.misa = Signal(32)
+        cl = []
+        for l in list(string.ascii_lowercase):
+            value = 1 if l == 'i' else 0
+            cl.append(Constant(value))
+        cl.append(Constant(0, 4))
+        cl.append(Constant(0b01, 2))
+        self.comb += self.misa.eq(Cat(cl))
+
 
 class CPU(Module):
     """
@@ -103,6 +156,23 @@ class CPU(Module):
                    Mux((dc.funct3[1]),
                        Constant(0b11, 2), Constant(0, 2)))
 
+    # XXX this happens to get done by various self.sync actions
+    #def reset_to_initial(self, m, mstatus, mie, registers):
+    #    return [m.mcause.eq(0),
+    #            ]
+
+    def write_register(self, register_number, value):
+        return If(register_number != 0,
+                  self.registers[register_number].eq(value)
+               )
+
+    def evaluate_csr_funct3_op(self, funct3, previous_value, written_value):
+        c = { "default": Constant(0, 32)}
+        for f in [F3.csrrw, F3.csrrwi]: c[f] = written_value
+        for f in [F3.csrrs, F3.csrrsi]: c[f] = written_value | previous_value
+        for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value
+        return Case(funct3, c)
+
     def __init__(self):
         self.clk = ClockSignal()
         self.reset = ResetSignal()
@@ -124,8 +194,10 @@ class CPU(Module):
 
         l = []
         for i in range(31):
-            l.append(Signal(32, name="register%d" % i))
-        registers = Array(l)
+            r = Signal(32, name="register%d" % i)
+            l.append(r)
+            self.sync += r.eq(Constant(0, 32))
+        self.registers = Array(l)
 
         mi = MemoryInterface()
 
@@ -197,11 +269,11 @@ class CPU(Module):
         self.comb += If(dc.rs1 == 0,
                         register_rs1.eq(0)
                      ).Else(
-                        register_rs1.eq(registers[dc.rs1-1]))
+                        register_rs1.eq(self.registers[dc.rs1-1]))
         self.comb += If(dc.rs2 == 0,
                         register_rs2.eq(0)
                      ).Else(
-                        register_rs2.eq(registers[dc.rs2-1]))
+                        register_rs2.eq(self.registers[dc.rs2-1]))
 
         load_store_address = Signal(32)
         load_store_address_low_2 = Signal(2)
@@ -326,14 +398,14 @@ class CPU(Module):
                                          branch_arg_a < branch_arg_b,
                                          branch_arg_a == branch_arg_b))
 
-        mcause = Signal(32)
-        mepc = Signal(32)
-        mscratch = Signal(32)
-        self.comb += mcause.eq(0)
-        self.comb += mepc.eq(0) # 32'hXXXXXXXX;
-        self.comb += mscratch.eq(0) # 32'hXXXXXXXX;
+        m = M(self.comb, self.sync)
+        mstatus = MStatus(self.comb, self.sync)
+        mie = MIE(self.comb, self.sync)
 
-        mstatus = MStatus(self.comb)
+        misa = Misa(self.comb, self.sync)
+
+        #self.sync += If(self.reset, self.reset_to_initial(m, mstatus, mie,
+        #                                                  registers))
 
 if __name__ == "__main__":
     example = CPU()
@@ -350,138 +422,6 @@ if __name__ == "__main__":
 
 """
 
-    reg mie_meie = 1'bX;
-    reg mie_mtie = 1'bX;
-    reg mie_msie = 1'bX;
-    parameter mie_seie = 0;
-    parameter mie_ueie = 0;
-    parameter mie_stie = 0;
-    parameter mie_utie = 0;
-    parameter mie_ssie = 0;
-    parameter mie_usie = 0;
-
-    task reset_to_initial;
-    begin
-        mcause = 0;
-        mepc = 32'hXXXXXXXX;
-        mscratch = 32'hXXXXXXXX;
-        mstatus_mie = 0;
-        mstatus_mpie = 1'bX;
-        mie_meie = 1'bX;
-        mie_mtie = 1'bX;
-        mie_msie = 1'bX;
-        registers['h01] <= 32'hXXXXXXXX;
-        registers['h02] <= 32'hXXXXXXXX;
-        registers['h03] <= 32'hXXXXXXXX;
-        registers['h04] <= 32'hXXXXXXXX;
-        registers['h05] <= 32'hXXXXXXXX;
-        registers['h06] <= 32'hXXXXXXXX;
-        registers['h07] <= 32'hXXXXXXXX;
-        registers['h08] <= 32'hXXXXXXXX;
-        registers['h09] <= 32'hXXXXXXXX;
-        registers['h0A] <= 32'hXXXXXXXX;
-        registers['h0B] <= 32'hXXXXXXXX;
-        registers['h0C] <= 32'hXXXXXXXX;
-        registers['h0D] <= 32'hXXXXXXXX;
-        registers['h0E] <= 32'hXXXXXXXX;
-        registers['h0F] <= 32'hXXXXXXXX;
-        registers['h10] <= 32'hXXXXXXXX;
-        registers['h11] <= 32'hXXXXXXXX;
-        registers['h12] <= 32'hXXXXXXXX;
-        registers['h13] <= 32'hXXXXXXXX;
-        registers['h14] <= 32'hXXXXXXXX;
-        registers['h15] <= 32'hXXXXXXXX;
-        registers['h16] <= 32'hXXXXXXXX;
-        registers['h17] <= 32'hXXXXXXXX;
-        registers['h18] <= 32'hXXXXXXXX;
-        registers['h19] <= 32'hXXXXXXXX;
-        registers['h1A] <= 32'hXXXXXXXX;
-        registers['h1B] <= 32'hXXXXXXXX;
-        registers['h1C] <= 32'hXXXXXXXX;
-        registers['h1D] <= 32'hXXXXXXXX;
-        registers['h1E] <= 32'hXXXXXXXX;
-        registers['h1F] <= 32'hXXXXXXXX;
-    end
-    endtask
-
-    task write_register(input [4:0] register_number, input [31:0] value);
-    begin
-        if(register_number != 0)
-            registers[register_number] <= value;
-    end
-    endtask
-
-    function [31:0] evaluate_csr_funct3_operation(input [2:0] funct3, input [31:0] previous_value, input [31:0] written_value);
-    begin
-        case(funct3)
-        `funct3_csrrw, `funct3_csrrwi:
-            evaluate_csr_funct3_operation = written_value;
-        `funct3_csrrs, `funct3_csrrsi:
-            evaluate_csr_funct3_operation = written_value | previous_value;
-        `funct3_csrrc, `funct3_csrrci:
-            evaluate_csr_funct3_operation = ~written_value & previous_value;
-        default:
-            evaluate_csr_funct3_operation = 32'hXXXXXXXX;
-        endcase
-    end
-    endfunction
-
-    parameter misa_a = 1'b0;
-    parameter misa_b = 1'b0;
-    parameter misa_c = 1'b0;
-    parameter misa_d = 1'b0;
-    parameter misa_e = 1'b0;
-    parameter misa_f = 1'b0;
-    parameter misa_g = 1'b0;
-    parameter misa_h = 1'b0;
-    parameter misa_i = 1'b1;
-    parameter misa_j = 1'b0;
-    parameter misa_k = 1'b0;
-    parameter misa_l = 1'b0;
-    parameter misa_m = 1'b0;
-    parameter misa_n = 1'b0;
-    parameter misa_o = 1'b0;
-    parameter misa_p = 1'b0;
-    parameter misa_q = 1'b0;
-    parameter misa_r = 1'b0;
-    parameter misa_s = 1'b0;
-    parameter misa_t = 1'b0;
-    parameter misa_u = 1'b0;
-    parameter misa_v = 1'b0;
-    parameter misa_w = 1'b0;
-    parameter misa_x = 1'b0;
-    parameter misa_y = 1'b0;
-    parameter misa_z = 1'b0;
-    parameter misa = {
-        2'b01,
-        4'b0,
-        misa_z,
-        misa_y,
-        misa_x,
-        misa_w,
-        misa_v,
-        misa_u,
-        misa_t,
-        misa_s,
-        misa_r,
-        misa_q,
-        misa_p,
-        misa_o,
-        misa_n,
-        misa_m,
-        misa_l,
-        misa_k,
-        misa_j,
-        misa_i,
-        misa_h,
-        misa_g,
-        misa_f,
-        misa_e,
-        misa_d,
-        misa_c,
-        misa_b,
-        misa_a};
-
     parameter mvendorid = 32'b0;
     parameter marchid = 32'b0;
     parameter mimpid = 32'b0;
-- 
2.30.2