From 23c6698ea29756de3f1bafdabd8b62af00404b4e Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Mon, 8 Jul 2019 23:43:34 +0200 Subject: [PATCH] radv/gfx10: Only set HW edge flags with gs & tess disabled. Reviewed-by: Dave Airlie --- src/amd/vulkan/radv_pipeline.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 1e7c25955fc..5751440f301 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3413,7 +3413,8 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, * flags in the shader. */ radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL, - S_028838_INDEX_BUF_EDGE_FLAG_ENA(1)); + S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) && + !radv_pipeline_has_gs(pipeline))); radeon_set_context_reg(ctx_cs, R_03096C_GE_CNTL, S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) | -- 2.30.2