From 23d889bcf1d34f9a9d28a7b18fca0179dcbb60db Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 6 Feb 2020 15:19:16 +0000 Subject: [PATCH] hdl.dsl: type check when adding to m.domains. --- nmigen/hdl/dsl.py | 7 +++++++ nmigen/test/test_hdl_dsl.py | 9 +++++++++ 2 files changed, 16 insertions(+) diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py index 8363737..aaecd9c 100644 --- a/nmigen/hdl/dsl.py +++ b/nmigen/hdl/dsl.py @@ -9,6 +9,7 @@ from .._utils import flatten, bits_for, deprecated from .. import tracer from .ast import * from .ir import * +from .cd import * from .xfrm import * @@ -107,10 +108,16 @@ class _ModuleBuilderDomainSet: def __iadd__(self, domains): for domain in flatten([domains]): + if not isinstance(domain, ClockDomain): + raise TypeError("Only clock domains may be added to `m.domains`, not {!r}" + .format(domain)) self._builder._add_domain(domain) return self def __setattr__(self, name, domain): + if not isinstance(domain, ClockDomain): + raise TypeError("Only clock domains may be added to `m.domains`, not {!r}" + .format(domain)) self._builder._add_domain(domain) diff --git a/nmigen/test/test_hdl_dsl.py b/nmigen/test/test_hdl_dsl.py index cc8467c..959c6e5 100644 --- a/nmigen/test/test_hdl_dsl.py +++ b/nmigen/test/test_hdl_dsl.py @@ -707,6 +707,15 @@ class DSLTestCase(FHDLTestCase): self.assertEqual(len(m._domains), 1) self.assertEqual(m._domains[0].name, "foo") + def test_domain_add_wrong(self): + m = Module() + with self.assertRaises(TypeError, + msg="Only clock domains may be added to `m.domains`, not 1"): + m.domains.foo = 1 + with self.assertRaises(TypeError, + msg="Only clock domains may be added to `m.domains`, not 1"): + m.domains += 1 + def test_lower(self): m1 = Module() m1.d.comb += self.c1.eq(self.s1) -- 2.30.2