From 23f5785a38edc44f7b5695edb7fd2f24c7355824 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 20 May 2018 12:43:09 +0100 Subject: [PATCH] update slides --- simple_v_extension/simple_v_chennai_2018.tex | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex index f8e2ee26e..f198fb9db 100644 --- a/simple_v_extension/simple_v_chennai_2018.tex +++ b/simple_v_extension/simple_v_chennai_2018.tex @@ -167,7 +167,12 @@ \item Please don't use Vectors for "security" (use Sec-Ext) \end{itemize} } - +% with overlapping "vectors" - bearing in mind that "vectors" are +% just a remap onto the standard register file, if the top bits of +% predication are zero, and there happens to be a second vector +% that uses some of the same register file that happens to be +% predicated out, the second vector op may be issued *at the same time* +% if there are available parallel ALUs to do so. \begin{frame}[fragile] \frametitle{ADD pseudocode (or trap, or actual hardware loop)} -- 2.30.2