From 23f9e6c6fa0accb4cda5a4c4c876bad1e08b2ff9 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 2 Sep 2021 13:23:36 +0100 Subject: [PATCH] --- openpower/sv/branches.mdwn | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn index cc9b91bd3..d4487dba9 100644 --- a/openpower/sv/branches.mdwn +++ b/openpower/sv/branches.mdwn @@ -91,8 +91,9 @@ Predication in both INT and CR modes may be applied to `sv.bc` and other SVP64 Branch Conditional operations, exactly as they may be applied to other SVP64 operations. When `sz` is zero, any masked-out Branch-element operations are not included in condition testing, exactly like all other -SVP64 operations. With one exception this *includes* side-effects such as potentially updating -LR and CTR which will also be skipped. The exception here is when +SVP64 operations, *including* side-effects such as potentially updating +LR or CTR, which will also be skipped. There is *one* exception here, +which is when `BO[2]=0, sz=0, CTR-test=0, CTi=1` and the relevant element predicate mask bit is also zero: under these special circumstances CTR will also decrement. -- 2.30.2