From 2403018690e8eda5c7b71c9f50416cf0a0840d67 Mon Sep 17 00:00:00 2001 From: Nils Asmussen Date: Sat, 21 Mar 2020 11:01:31 +0100 Subject: [PATCH] cpu,configs: let RISC-V use the PT walker cache. Change-Id: I19b1dd9e3c55c433c897988d36e6715017273c66 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26988 Tested-by: kokoro Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com> Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- configs/common/CacheConfig.py | 5 +++-- configs/common/Caches.py | 3 ++- src/cpu/BaseCPU.py | 5 +++-- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index 91087fb82..05c38e011 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -1,4 +1,5 @@ # Copyright (c) 2012-2013, 2015-2016 ARM Limited +# Copyright (c) 2020 Barkhausen Institut # All rights reserved # # The license below extends only to copyright in the software and shall @@ -79,7 +80,7 @@ def config_cache(options, system): dcache_class, icache_class, l2_cache_class, walk_cache_class = \ L1_DCache, L1_ICache, L2Cache, None - if buildEnv['TARGET_ISA'] == 'x86': + if buildEnv['TARGET_ISA'] in ['x86', 'riscv']: walk_cache_class = PageTableWalkerCache # Set the cache line size of the system @@ -181,7 +182,7 @@ def config_cache(options, system): # on these names. For simplicity, we would advise configuring # it to use this naming scheme; if this isn't possible, change # the names below. - if buildEnv['TARGET_ISA'] in ['x86', 'arm']: + if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']: system.cpu[i].addPrivateSplitL1Caches( ExternalCache("cpu%d.icache" % i), ExternalCache("cpu%d.dcache" % i), diff --git a/configs/common/Caches.py b/configs/common/Caches.py index 123fea453..77213e8ee 100644 --- a/configs/common/Caches.py +++ b/configs/common/Caches.py @@ -1,4 +1,5 @@ # Copyright (c) 2012 ARM Limited +# Copyright (c) 2020 Barkhausen Institut # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -92,7 +93,7 @@ class PageTableWalkerCache(Cache): tgts_per_mshr = 12 # the x86 table walker actually writes to the table-walker cache - if buildEnv['TARGET_ISA'] == 'x86': + if buildEnv['TARGET_ISA'] in ['x86', 'riscv']: is_read_only = False else: is_read_only = True diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 53652bfc3..67d95d0f4 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -1,4 +1,5 @@ # Copyright (c) 2012-2013, 2015-2017 ARM Limited +# Copyright (c) 2020 Barkhausen Institut # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -181,7 +182,7 @@ class BaseCPU(ClockedObject): dcache_port = MasterPort("Data Port") _cached_ports = ['icache_port', 'dcache_port'] - if buildEnv['TARGET_ISA'] in ['x86', 'arm']: + if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']: _cached_ports += ["itb.walker.port", "dtb.walker.port"] _uncached_slave_ports = [] @@ -216,7 +217,7 @@ class BaseCPU(ClockedObject): self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] - if buildEnv['TARGET_ISA'] in ['x86', 'arm']: + if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']: if iwc and dwc: self.itb_walker_cache = iwc self.dtb_walker_cache = dwc -- 2.30.2