From 2406084c62af6bb414024d176331d480c08e99cd Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 28 Jan 2021 22:59:33 +0000 Subject: [PATCH] --- openpower/sv/bitmanip.mdwn | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn index 79f099adb..112ed6247 100644 --- a/openpower/sv/bitmanip.mdwn +++ b/openpower/sv/bitmanip.mdwn @@ -155,6 +155,22 @@ signed and unsigned min/max for integer. this is sort-of partly synthesiseable signed/unsigned min/max gives more flexibility. +``` +uint_xlen_t min(uint_xlen_t rs1, uint_xlen_t rs2) +{ return (int_xlen_t)rs1 < (int_xlen_t)rs2 ? rs1 : rs2; +} +uint_xlen_t max(uint_xlen_t rs1, uint_xlen_t rs2) +{ return (int_xlen_t)rs1 > (int_xlen_t)rs2 ? rs1 : rs2; +} +uint_xlen_t minu(uint_xlen_t rs1, uint_xlen_t rs2) +{ return rs1 < rs2 ? rs1 : rs2; +} +uint_xlen_t maxu(uint_xlen_t rs1, uint_xlen_t rs2) +{ return rs1 > rs2 ? rs1 : rs2; +} +``` + + # ternary bitops Similar to FPGA LUTs: for every bit perform a lookup into a table using an 8bit immediate, or in another register -- 2.30.2