From 2412650f560e295973a8856917c6588add004c7e Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Fri, 28 Dec 2018 02:10:15 -0500 Subject: [PATCH] hdl.dsl: Support Assert and Assume where an Assign can occur. --- nmigen/__init__.py | 2 +- nmigen/hdl/dsl.py | 4 ++-- nmigen/test/test_hdl_dsl.py | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/nmigen/__init__.py b/nmigen/__init__.py index 220f5bb..613cb50 100644 --- a/nmigen/__init__.py +++ b/nmigen/__init__.py @@ -1,4 +1,4 @@ -from .hdl.ast import Value, Const, C, Mux, Cat, Repl, Array, Signal, ClockSignal, ResetSignal +from .hdl.ast import Value, Const, C, Mux, Cat, Repl, Array, Signal, ClockSignal, ResetSignal, Assert, Assume from .hdl.dsl import Module from .hdl.cd import ClockDomain from .hdl.ir import Fragment, Instance diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py index 944a3ec..968f396 100644 --- a/nmigen/hdl/dsl.py +++ b/nmigen/hdl/dsl.py @@ -336,9 +336,9 @@ class Module(_ModuleBuilderRoot): self._pop_ctrl() for assign in Statement.wrap(assigns): - if not compat_mode and not isinstance(assign, Assign): + if not compat_mode and not isinstance(assign, (Assign, Assert, Assume)): raise SyntaxError( - "Only assignments may be appended to d.{}" + "Only assignments, asserts, and assumes may be appended to d.{}" .format(domain_name(domain))) for signal in assign._lhs_signals(): diff --git a/nmigen/test/test_hdl_dsl.py b/nmigen/test/test_hdl_dsl.py index 43c9672..2a33864 100644 --- a/nmigen/test/test_hdl_dsl.py +++ b/nmigen/test/test_hdl_dsl.py @@ -74,7 +74,7 @@ class DSLTestCase(FHDLTestCase): def test_d_asgn_wrong(self): m = Module() with self.assertRaises(SyntaxError, - msg="Only assignments may be appended to d.sync"): + msg="Only assignments, asserts, and assumes may be appended to d.sync"): m.d.sync += Switch(self.s1, {}) def test_comb_wrong(self): -- 2.30.2