From 2424648be3920c8c38b8a0e57887c5571ebebe4d Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 29 Jan 2021 19:10:55 +0000 Subject: [PATCH] --- openpower/sv/setvl.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn index 190dbafe9..e2d2f3de7 100644 --- a/openpower/sv/setvl.mdwn +++ b/openpower/sv/setvl.mdwn @@ -47,7 +47,7 @@ Form: SVL-Form (see [[isatables/fields.text]]) | -- | -- | --- | ------ | ------ | ------- |--| ------- | | 19 | RT | RA | SVi // | vs ms | XO[0:4] |Rc| setvl | -Note that imm (SVi) spans 7 bits (16 to 22), and that bit 22 and 23 is reserved and must be zero. Setting bit 22 or 23 causes an illegal exception. +Note that the immediate (`SVi`) spans 7 bits (16 to 22), and that bit 22 and 23 is reserved and must be zero. Setting bit 22 or 23 causes an illegal exception. `ms` - bit 25 - allows for setting of MVL. `vs` - bit 24 - allows for setting of VL. -- 2.30.2