From 243e240ee3823d6124dd30ae46671da8311c6b9a Mon Sep 17 00:00:00 2001 From: Ian Jiang Date: Tue, 18 Aug 2020 17:19:36 +0800 Subject: [PATCH] arch-riscv: Fix disassembling of CSR instructions The correct formats of CSR instructions are: - mnemonic rd, csr, rs1 - mnemonic rd, csr, uimm This patch fixes the problem. Change-Id: Ie34e67a523e3458b90c27ca19f8c660b4775da6f Signed-off-by: Ian Jiang Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32814 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- src/arch/riscv/insts/standard.cc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/arch/riscv/insts/standard.cc b/src/arch/riscv/insts/standard.cc index 9a9aa9da4..35f9ccd4b 100644 --- a/src/arch/riscv/insts/standard.cc +++ b/src/arch/riscv/insts/standard.cc @@ -60,13 +60,15 @@ CSROp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { stringstream ss; ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "; - if (_numSrcRegs > 0) - ss << registerName(_srcRegIdx[0]) << ", "; auto data = CSRData.find(csr); if (data != CSRData.end()) ss << data->second.name; else - ss << "?? (" << hex << "0x" << csr << ")"; + ss << "?? (" << hex << "0x" << csr << dec << ")"; + if (_numSrcRegs > 0) + ss << ", " << registerName(_srcRegIdx[0]); + else + ss << uimm; return ss.str(); } -- 2.30.2