From 246b860a8550a3972bfb63d50a8656e02e8cdebe Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 28 Jul 2013 16:33:36 +0200 Subject: [PATCH] csr: new data width API --- migen/bank/csrgen.py | 14 ++++++++------ migen/bus/csr.py | 22 ++++++++++++---------- migen/bus/wishbone2csr.py | 14 +++++++++----- 3 files changed, 29 insertions(+), 21 deletions(-) diff --git a/migen/bank/csrgen.py b/migen/bank/csrgen.py index 836a499e..3624d90d 100644 --- a/migen/bank/csrgen.py +++ b/migen/bank/csrgen.py @@ -21,7 +21,7 @@ class Bank(Module): if isinstance(c, CSR): simple_csrs.append(c) else: - c.finalize(csr.data_width) + c.finalize(flen(self.bus.dat_w)) simple_csrs += c.get_simple_csrs() self.submodules += c nbits = bits_for(len(simple_csrs)-1) @@ -53,12 +53,12 @@ class Bank(Module): # address_map is called exactly once for each object at each call to # scan(), so it can have side effects. class BankArray(Module): - def __init__(self, source, address_map): + def __init__(self, source, address_map, *ifargs, **ifkwargs): self.source = source self.address_map = address_map - self.scan() + self.scan(ifargs, ifkwargs) - def scan(self): + def scan(self, ifargs, ifkwargs): self.banks = [] self.srams = [] for name, obj in sorted(self.source.__dict__.items(), key=itemgetter(0)): @@ -70,13 +70,15 @@ class BankArray(Module): memories = obj.get_memories() for memory in memories: mapaddr = self.address_map(name, memory) - mmap = csr.SRAM(memory, mapaddr) + sram_bus = csr.Interface(*ifargs, **ifkwargs) + mmap = csr.SRAM(memory, mapaddr, bus=sram_bus) self.submodules += mmap csrs += mmap.get_csrs() self.srams.append((name, memory, mapaddr, mmap)) if csrs: mapaddr = self.address_map(name, None) - rmap = Bank(csrs, mapaddr) + bank_bus = csr.Interface(*ifargs, **ifkwargs) + rmap = Bank(csrs, mapaddr, bus=bank_bus) self.submodules += rmap self.banks.append((name, csrs, mapaddr, rmap)) diff --git a/migen/bus/csr.py b/migen/bus/csr.py index 5843d015..699228bf 100644 --- a/migen/bus/csr.py +++ b/migen/bus/csr.py @@ -4,15 +4,16 @@ from migen.bank.description import CSRStorage from migen.genlib.record import * from migen.genlib.misc import chooser -data_width = 8 +_layout = [ + ("adr", 14, DIR_M_TO_S), + ("we", 1, DIR_M_TO_S), + ("dat_w", "data_width", DIR_M_TO_S), + ("dat_r", "data_width", DIR_S_TO_M) +] class Interface(Record): - def __init__(self): - Record.__init__(self, [ - ("adr", 14, DIR_M_TO_S), - ("we", 1, DIR_M_TO_S), - ("dat_w", data_width, DIR_M_TO_S), - ("dat_r", data_width, DIR_S_TO_M)]) + def __init__(self, data_width=8): + Record.__init__(self, _layout, data_width=data_width) class Interconnect(Module): def __init__(self, master, slaves): @@ -55,6 +56,10 @@ class Initiator(Module): class SRAM(Module): def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None): + if bus is None: + bus = Interface() + self.bus = bus + data_width = flen(self.bus.dat_w) if isinstance(mem_or_size, Memory): mem = mem_or_size else: @@ -71,9 +76,6 @@ class SRAM(Module): read_only = mem.bus_read_only else: read_only = False - if bus is None: - bus = Interface() - self.bus = bus ### diff --git a/migen/bus/wishbone2csr.py b/migen/bus/wishbone2csr.py index 5b803787..7a273c2c 100644 --- a/migen/bus/wishbone2csr.py +++ b/migen/bus/wishbone2csr.py @@ -4,16 +4,20 @@ from migen.bus import csr from migen.genlib.misc import timeline class WB2CSR(Module): - def __init__(self): - self.wishbone = wishbone.Interface() - self.csr = csr.Interface() + def __init__(self, bus_wishbone=None, bus_csr=None): + if bus_wishbone is None: + bus_wishbone = wishbone.Interface() + self.wishbone = bus_wishbone + if bus_csr is None: + bus_csr = csr.Interface() + self.csr = bus_csr ### self.sync += [ self.csr.we.eq(0), - self.csr.dat_w.eq(self.wishbone.dat_w[:csr.data_width]), - self.csr.adr.eq(self.wishbone.adr[:14]), + self.csr.dat_w.eq(self.wishbone.dat_w), + self.csr.adr.eq(self.wishbone.adr), self.wishbone.dat_r.eq(self.csr.dat_r) ] self.sync += timeline(self.wishbone.cyc & self.wishbone.stb, [ -- 2.30.2