From 249cb511c54d40a762c862a7e378a362db4a1ca0 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Tue, 17 Dec 2013 00:46:45 +0100 Subject: [PATCH] radeonsi: flush HTILE when appropriate MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Michel Dänzer --- src/gallium/drivers/radeonsi/r600_hw_context.c | 1 + src/gallium/drivers/radeonsi/si_state.c | 3 ++- src/gallium/drivers/radeonsi/si_state_draw.c | 6 +++++- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/r600_hw_context.c b/src/gallium/drivers/radeonsi/r600_hw_context.c index 3003dad5e8a..c21a1013f93 100644 --- a/src/gallium/drivers/radeonsi/r600_hw_context.c +++ b/src/gallium/drivers/radeonsi/r600_hw_context.c @@ -197,6 +197,7 @@ void si_context_flush(struct r600_context *ctx, unsigned flags) ctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB | R600_CONTEXT_FLUSH_AND_INV_CB_META | R600_CONTEXT_FLUSH_AND_INV_DB | + R600_CONTEXT_FLUSH_AND_INV_DB_META | R600_CONTEXT_INV_TEX_CACHE; si_emit_cache_flush(&ctx->b, NULL); diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 9b9e9737111..ede8827fe47 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2099,7 +2099,8 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, R600_CONTEXT_FLUSH_AND_INV_CB_META; } if (rctx->framebuffer.zsbuf) { - rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB; + rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB | + R600_CONTEXT_FLUSH_AND_INV_DB_META; } util_copy_framebuffer_state(&rctx->framebuffer, state); diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 63df3b555c3..a3104d0a266 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -676,6 +676,10 @@ void si_emit_cache_flush(struct r600_common_context *rctx, struct r600_atom *ato radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0)); } + if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB_META) { + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); + } if (rctx->flags & R600_CONTEXT_WAIT_3D_IDLE) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); @@ -689,7 +693,7 @@ void si_emit_cache_flush(struct r600_common_context *rctx, struct r600_atom *ato rctx->flags = 0; } -const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 11 }; /* number of CS dwords */ +const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 13 }; /* number of CS dwords */ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) { -- 2.30.2