From 24ba00401c459ed36156b93f2e08823d1d960ff3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 10 Jul 2022 13:59:26 +0100 Subject: [PATCH] fix svindex unit test, experiment setting dimensions to 0b111111 in svindex pseudocode --- openpower/isa/simplev.mdwn | 10 ++++++---- src/openpower/decoder/isa/svshape.py | 9 ++++----- .../decoder/isa/test_caller_svindex.py | 18 ++++++++++++------ 3 files changed, 22 insertions(+), 15 deletions(-) diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn index fd3ed3b5..8e31fc0f 100644 --- a/openpower/isa/simplev.mdwn +++ b/openpower/isa/simplev.mdwn @@ -279,12 +279,14 @@ Pseudo-code: shape[30:31] <- 0b00 # mode if yx = 0 then shape[18:20] <- 0b110 # indexed xd/yd - shape[0:5] <- 0 # xdim - shape[6:11] <- (0b0 || SVd) # ydim + shape[0:5] <- (0b0 || SVd) # xdim + if sk = 1 then shape[6:11] <- 0 # ydim + else shape[6:11] <- 0b111111 # ydim max else shape[18:20] <- 0b111 # indexed yd/xd - shape[0:5] <- (0b0 || SVd) # xdim - shape[6:11] <- 0 # ydim + if sk = 1 then shape[0:5] <- 0 # xdim + else shape[0:5] <- 0b111111 # xdim max + shape[6:11] <- (0b0 || SVd) # ydim shape[12:17] <- (0b0 || SVG) # SVGPR shape[28:29] <- ew # element-width override if sk = 1 then shape[28:29] <- 0b01 # skip 1st dimension diff --git a/src/openpower/decoder/isa/svshape.py b/src/openpower/decoder/isa/svshape.py index 7e9ad322..dbddd5db 100644 --- a/src/openpower/decoder/isa/svshape.py +++ b/src/openpower/decoder/isa/svshape.py @@ -179,8 +179,8 @@ class SVSHAPE(SelectableInt): if __name__ == '__main__': os.environ['SILENCELOG'] = "1" - xdim = 2 - ydim = 3 + xdim = 3 + ydim = 2000 zdim = 1 SVSHAPE0 = SVSHAPE(0) SVSHAPE0.lims = [xdim, ydim, zdim] @@ -188,9 +188,9 @@ if __name__ == '__main__': SVSHAPE0.mode = 0b00 SVSHAPE0.skip = 0b00 SVSHAPE0.offset = 0 # experiment with different offset, here - SVSHAPE0.invxyz = [0,0,1] # inversion if desired + SVSHAPE0.invxyz = [0,0,1] # xy inversion (indices 0,1) , skip if desired (2) - VL = xdim * ydim * zdim + VL = 6 # xdim * ydim * zdim print ("Matrix Indexed Mode", SVSHAPE0.order, SVSHAPE0.invxyz) for idx, new_idx in enumerate(SVSHAPE0.get_iterator()): @@ -200,7 +200,6 @@ if __name__ == '__main__': print ("") - xdim = 3 ydim = 2 zdim = 1 diff --git a/src/openpower/decoder/isa/test_caller_svindex.py b/src/openpower/decoder/isa/test_caller_svindex.py index 13d651fc..6912707c 100644 --- a/src/openpower/decoder/isa/test_caller_svindex.py +++ b/src/openpower/decoder/isa/test_caller_svindex.py @@ -72,6 +72,11 @@ class SVSTATETestCase(FHDLTestCase): print (" mi1", bin(sim.svstate.mi1)) print (" mi2", bin(sim.svstate.mi2)) print ("STATE0svgpr", hex(SVSHAPE0.svgpr)) + print ("STATE0 xdim", SVSHAPE0.xdimsz) + print ("STATE0 ydim", SVSHAPE0.ydimsz) + print ("STATE0 skip", bin(SVSHAPE0.skip)) + print ("STATE0 inv", SVSHAPE0.invxyz) + print ("STATE0order", SVSHAPE0.order) self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0 self.assertEqual(sim.svstate.SVme, 0b01111) # same as rmm # rmm is 0b01111 which means mi0=0 mi1=1 mi2=2 mo0=3 mo1=0 @@ -89,7 +94,7 @@ class SVSTATETestCase(FHDLTestCase): only RA is re-mapped via Indexing, not RB or RT """ - isa = SVP64Asm(['svindex 8, 1, 3, 0, 0, 0, 0', + isa = SVP64Asm(['svindex 8, 1, 6, 0, 0, 0, 0', 'sv.add *8, *0, *0', ]) lst = list(isa) @@ -111,14 +116,14 @@ class SVSTATETestCase(FHDLTestCase): # copy before running expected_regs = deepcopy(initial_regs) for i in range(6): - RA = initial_regs[16+idxs[i]] - RB = initial_regs[16+i] + RA = initial_regs[0+idxs[i]] + RB = initial_regs[0+i] expected_regs[i+8] = RA+RB print ("expected", i, expected_regs[i+8]) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) - #self._check_regs(sim, expected_regs) + self._check_regs(sim, expected_regs) print (sim.spr) SVSHAPE0 = sim.spr['SVSHAPE0'] @@ -144,9 +149,10 @@ class SVSTATETestCase(FHDLTestCase): self.assertEqual(sim.svstate.mi2, 0) self.assertEqual(sim.svstate.mo0, 0) self.assertEqual(sim.svstate.mo1, 0) - for i in range(4): + self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1 + for i in range(1,4): shape = sim.spr['SVSHAPE%d' % i] - self.assertEqual(shape.svgpr, 16) # SVG is shifted up by 1 + self.assertEqual(shape.svgpr, 0) def run_tst_program(self, prog, initial_regs=None, svstate=None): -- 2.30.2